Static timing analysis interview questions

1. Introduction: Hello, everyone. Welcome to static timing analysis, interview questions. This is the part one of the series, and today we'll be covering some of the basic interview questions for static timing analysis. Let us begin. Before we start the course, let us look at some of the course requirements. You need to have a basic STA background. So digital design concepts will be helpful, and some timing analysis knowledge will help you in understanding the course. Let us look at deco structure. Dec structure is split into four parts. The first part is covering the SDA flow interview questions. The second part is covering the timing arc interview questions. The third part is the important setup and hold interview questions, and the last part is discussing about the reset and clock getting interview questions. Coming to the course objectives, the course is to help students currently having basic skills in static timing analysis and physical design to quickly ramp up for a interview. If you have been following my LinkedIn profile, I have been regularly publishing daily interview questions on SDA to help cover broad range of concepts. So let us not waste any time and begin the learning journey. Thank you. 2. STA flow interview questions: Hello, everyone. Welcome to the STA interview series. The first part is introduction to STA and flow. Let us begin. To begin this course, let us understand how the STA flow works and wherein the ASAC design flow STA is used. Basically, you have the RTL designer who writes the RTL and it is verified with a test pinch by design verification engineer. Then it goes through a logic synthesis and DFT insertion. After these two stages, a prelaud STA is performed. This may not be with the accurate delay information. This has an input of the design constraints and approximated delay model, which will help to do a first STA on your design. Once the design is synthesized, it goes to the back end engineer for floor planning and clock ti synthesis. After floor planning and clock synthesis, we do another round of an STA analysis. This is basically with the estimated parasitics. You'll still have the constraints from your design and you will do an STA. This is not considered as a sign off because this is with the estimated paraetics. After you do a place and route, you have the real delay information with the SDF format. And this delay information is fed to the SDA engine, and with the extracted parasitic information and with the constraints, the tool will do a timing analysis on your design, and it will generate a report. Now let us try to see what are the inputs and outputs of a SDA tool. The STA tool needs the delay information, which is either in the SDF standard delay format or the SPF format. It then needs the gate level Netlist. This will be the Netlist, that is synthesized from your RTL. Then it needs the SDC, which is the delay constraints. It's the design constraints for your design, and then it needs the library information. The library information contains the cell delays, and then it generates the timing report and the timing window. Now that we know where as design flow STA is performed and the inputs and outputs for an STA engine, we'll try to understand what are the types of checks that are performed in the STA. We have the setup and hold check. We have the reset and removal check. We have the cloggeting checks. We have minimum period and pulse width of clock checks, and we have some design rules checks which are performed in the STA. We will discuss this in detail in the coming lectures. Now that we saw the checks that are performed in STA, we'll try to see one of the files that is used as an input for your STA engine, which is the SDF file. What is an SDF file and what does it contain? So the SDF file contains the delay information. The delays like module, part delay, device delay, interconnect delay, port delay are all contained in your SDF file. Then you have the timing checks set up and hold, recovery, removal, skew width, period are part of your SDF file. Then you have timing constraints, then you have timing environments, which is the intended operating timing environment. And then you have incremental and absolute delays. We'll try to see what is contained in SDF file in an example in the next slide. Here is a SDF example for a cell. The cell here is a deflp flop. This contains as I mentioned in the last slide, it has the delay information. Here you have two parts, which is the clock to Q and clock R set to Q, and this is containing the minin max delays for these parts. And then we have the timing check. The timing check section entry specify the limits in the way in which the signal can change or two signals can change in relation to each other. For a reliable circuit operation, these timing checks has to hold. The EDA tools use this information in different ways. The simulation tools issues warnings when signal transition violate these timing checks. The timing analysis tools identify the delay parts that may cause timing check violation and may determine the constraints for these parts. Thank you. 3. STA Timing arcs: Welcome back to the STA interview question series. This is the Chapter two of the series, and we will be discussing about the timing arcs in circuits. Let us begin. So what are the different timing arcs in the circuit? You have the cell arcs and you have the net arcs. The cell arcs are basically the arcs inside the cells in your design. The net arcs are usually the arcs that are connecting the two cells in your design. Let us discuss this in detail in our next slides. The next question is what is unitness in a timing arc? We have three types of units. You have the positive unit, you have the negative unit, and you have a non unit. A positive unit timing arc is if a rising edge in an input causes a rising edge in an output or no change in an output, it is called a positive unit or a falling edge in an input causes a falling edge on the output or no change on the output, it is called a positive unit. A negative unit, as you imagine, is just the opposite. A rising edge on an input causes falling edge on an output or no change in output or a falling edge on the input causes, rising edge on the output or no change on the output. It is called a negative unit. The third type is the non unit. The non unit is basically a change of output cannot be determined by change in input. Let us see the examples for all the different types. Oh good example for a positive and a negative unit is a buffer and inverter. What happens in a buffer? A rising edge in an input causes rising edge in output. It's a positive unit. A falling edge causes a falling GND outputs. It's a positive unit. Similarly, for an inverter, a rising edge causes a falling GND output, and a falling edge in D input causes a rising GND output. It's a negative unit. Let us see other examples in the coming slides. So the next question is, is an digit a positive unit or a negative unit? Let us try to understand. So for instance, here, you have a rising edge on input A. Assume B is one, then you have a rising edge on a output, and assume B is zero, the output is no change, so it's a positive unit. Similarly for the arc here, you have a rising edge on B, if A is kept constant or if kept zero, then you have no change. If A is kept to one, then the output is a rising edge. It's a positive unit. It's the same case for the falling edge. You have a falling edge. I output is no change, that is a B to zero, then you hit the output is constant. If B is one, then you have a falling edge. It is the same for this arc. Gate is a positive unit. In the last slide, we saw an example of an gate which is a positive unit. Let us now see an Rgate. What happens in an argate When you have a rising edge in A, you have a falling edge in B, if B is zero. Se, if B is one, the output remains unchanged. So it's a negative unit. It's the same logic for this arc. You have a rising edge and if A is zero, you have a falling edge. If A is one, there is no change. This is a negative unit. It's the same for falling edge. For the falling edge, you have a rising edge if B zero, and you have no change if B is one, your Nargt is a negative unit. R is a positive unit and Nand N R is a negative unit. Let us see in the next slide what happens when we take the XR example. So let us see the example for an XOR gate. When there's a rising edge on A, when B is zero, you have a falling edge and when B is one, you have a rising edge. The same case for the B input when you have P at one and when A is zero, you have a falling edge and when A is one, you have a rising edge. What does this conclude? There is no clear relation between the input and output here. XR is a non unit. It's the same case for the falling edge. For the falling edge, you have a rising edge one B zero and falling edge one B is one. XOR gate is considered as a non unit. Let us see where this uniteness is used in STA. So in the previous slide, we discussed the different unit concepts. We'll try to see where this is used. The unit concept is used in the dot lip file or the timing file. So if you open a dot lip file for a buffer, you will see the timing sense that is for A two, Y, that is output and the related pin is A, it is shown that it's a positive unit. Similarly, this is an digit example. Here you have A to Y, that is a pin, which is a positive unit, and B to Y, as we saw for an digit is also a positive unit. In the previous slides, we understood the concept of uniteness. Now we will try to understand the different paths that are used for timing analysis. We have the data path, the clock path, the clock getting path and the asynchronous path. I will show each of these in detail in the coming slides. So the next question is, what are the different data paths? The different data paths are basically you have input port to a register that is this path here. You have registered to register, that is clock to Q. You have registered to output path, that is from here to here, and you have a path from the input port to the output port. These are the different data paths. So what are the different clock paths? The different clock paths here is a clock path from here to the from the input port to your clock pin. Basically, there might be many buffers between these signals going from the input port to your clock pin. Here in this slide, there are two clock paths. The next question is on the cloggeting path. Many times in your design, you may need to get clocks to reduce dynamic power consumption. Here in this circuit, you have this LD, which is a clock getting signal for this clock. LD is not part of any clock, but it is used for getting this clock. So it is used as a clog getating path. The last path is the asynchronous path. Here we see an asynchronous path from your reset pin to your reset of your flip flop. In today's lecture, we discussed about the timing arcs and the different data paths. In the next lecture, we will see how a setup and hold violation occurs and what are the equations to solve setup and hole problems. Thank you. 4. Setup and hold: Welcome to the Chapter three of the STA interview question series. Let us begin. I assume by now most of you would have known what a setup time or a whole time is, but you're still not aware, I'll try to explain briefly. Setup time is a time before the clock edge by which the data to the flip flop has to be stable. And whole time is basically a time window after the clock edge, that the data has to be stable. Any violation between these two window will create a metastability. So let us uncover setup and whole concepts using this diagram here. Here you have a launching flop and a capturing flop. The data that is launched onto the launching flop goes through a combinational path and then reaches the capturing flop. Data has to reach before the setup time before the clock edge, and it has to be held stable for whole time after the clock edge. What happens if a setup or whole violation occurs, the circuit goes into metastability. To avoid metastability, we need to make sure that the setup and whole times are always respected. Let us see an equation on how to calculate the setup and whole time. You have here you have the T clock to Q delay. This is the delay that is for the data to be launched from this flip flop, then you have the propagation delay. The propagation delay is basically the time, it takes for the logic to propagate from this node to this node. You have the setup time, which needs to be basically honored for this particular flip clop or this particular circuit. You have the clock sku. Clock queue is basically the difference in the clock reaching this node to this node. Addition of all this should be less than the total time period. Let us see the equation now for the whole time. You have the clock to Q here and you have the propagation delay here. This has to be held stable for T hold plus T sq. This will give us an equation for so this gives us the equation for the setup slack. Setup slack is basically a T period minus T clock plus T prop plus D setup, minus TQ. A positive setup slack means the D circuit is not metastable. And this is a similar equation for the hold slack. Hold Slack is basically T clock plus T prop minus T hole plus T sq. If the hold slack is positive, that means there's still some margin available in the timing path. Let us see some of the interview questions based on this concept. So coming to an interview question, an interviewer may ask you, how do you tackle a setup violation in your circuit? This is based on your setup slack equation. The setup slack is basically T period minus T clock to Q plus, T prop plus T setup minus TsQ so a setup slack has to be positive to avoid metastability in your circuit. So how can this be done? This can either be done by increasing the T period, which is indirectly reducing the clock frequency that you time your circuit, or you have to either play around with these things. That is, decrease the clock to queue or decrease the propagation delay of your combinational path, reduce the setup time requirement of the capturing flop, or increase the clocks Queue between the capture and launch clocks. So these are the ways to tackle setup violation. We saw in the last slide, some of the approaches to a setup violation. Let us see in a real scenario how this is done. One of the approaches is to increase the drive strength of the data path logic. A cell with better drive stenth can charge the load capacitance quickly, resulting in the lesser propagation delay. You three prop produces and your setup slack turns positive. Use data part cells with lesser threshold voltage. Usually in your cell library, there are the same cells with different threshold voltages. So if you use cells with a lesser threshold voltage, it will have a lesser delay. Another approach is to restructure the data path. Based on the placement of data path cells, you can decide to either combine logic gates or split into multi stage cell so that the propagation delay can be reduced. Another way is to play with the T clock. As a last resort, what you would probably do is time your design at a reduced frequency. So in the last two slides we saw how to tackle setup violation. Now we will see how a hold violation can be tackled. A hold slack is basically T clock to Q plus T minus T hold minus T q. So to have a positive hold slack, you can increase the clock to Q delay of the launching flop, decrease the holding requirement, decrease the clock squeue between the capturing clock and the launching flop or increase the propagation delay. So we will see some of the examples on how to do this in the real world scenario. As we saw, we need to increase the propagation delay for to fix a hold violation. What do you do? You basically insert delay elements. This is the simplest that you can do to remove hold violations. Another way is reduce drive strength of the data path. Replace the cell with a similar cell of less drive strength. This will increase the propagation delay of the cell. And the other approach is, as we saw in setup, we use cells with lower threshold voltages. For whole violations, we need to use cells with higher threshold voltages so that the propagation delay increases. Thank you. Another common interview question is, what is false path in your design? False paths are basically paths that are not timed in your STA. This may not be time for different reasons. One of the reasons may be that path is not possible architecturally. For example, if you take a max, here you have a select which is selecting the max and which is also input for Mx one. When select is zero, this path is not at all possible architecturally. You can set a false path on this design. Another interview question that is asked is usually on the setup and hold time. For that, you need to remember the setup slack and D hold slack equation. So if the setup slack and hold slack is positive, that means there is no setup or hole violation. From the figure above, the T period is 10 nanoseconds. Clock to Q is two, T prop max is four, T setup is one and Ts is one. If you calculate here, the setup slack comes out two plus four nanosecond. So there is no setup violation. Similarly, for the whole slack, you have clock to Q, T prop, T hold, and TQ. So the whole slack is also positive. This circuit is timing clean. This brings us to the end of part one of the digital design log interview questions. Thank you for your time. 5. Reset and clock gating interview questions : Welcome to the Chapter four of the SDA interview questions. Today I'll be discussing about the reset and log getating. Let us begin. Coming to the question, first question, what are the different types of reset? You have the synchronous reset and you have the asynchronous reset. If the reset affects the state of the design, only on the active edge of the clock, we term it as a synchronous reset. If the reset affects the state of this design asynchronously, that is whether there is a clock running or not running, then the design is sent to have asynchronous reset. One important point to note is, we cannot afford to have glitches in the reset signal as long as it is meeting the setup and whole timing. So if a reset signal is generated by a set of internal logic signals in your design, synchronouse reset is the only go to options. As there will be glitches formed by mingling of the different conditions. For the designs with asynchronous reset, datapath is independent of the reset signal. Logic levels in datapath are less. This means that we can achieve higher frequency using asynchronous resets. The design can be reset even when clock is gated. Also, there is no workarounds needed during synthesis as in case of the synchronous reset. The only condition for an asynchronous reset is it needs to be glitch free. Even a small glitch on the reset can reset the design. We saw in the previous slide, what is the difference between a synchronous end asynchronous reset. What are the things to note during a async reset Dassertion? For a flip flop with asynchronous reset, assertion of resets Diplo asynchronous. The deassertion of reset leaves the output of the flip flop unchanged. The state of the flip flop will change only on the arrival of the next clock pulse. There are two scenarios here. The clock is gregtd during the deassertion of reset. The clock is running during the deassertion of reset. In the case of clock deassertion clock is gated during the deer session of reset. In this case, we can safely deassert reset and ungate the clock after the deassertion. If the clock is running during the de session, in this case, we need to take care of the recovery and removal timing of the dessertion of reset. The deassertion of reset must be synchronouse with respect to the clock and reset synchronizers are needed in this case. So how are most designs modeled? Most designs are modeled to have asynchronous reset assertion and a synchronous reset de assertion. In which case, you need a reset synchronizer. We will discuss this in detail in the next slide. So what is a reset synchronizer? A reset synchronizer is basically used to model the behavior that I described in the previous slide. That is asynchronous reset assertion and synchronous reset de assertion. Here you have a clock and then asynchronous reset. When you have an asynchronous reset here, the reset synchronous or output is basically it combinationly causes the output to go to zero because this register is reset and this will reset the functional registers here. So reset assertion will asynchronously reset the registers. Let us now consider the reset deassertion case. When the reset is deasserted that is here, you have the deassertion here. It will wait for the clockage here. Basically, on the first clock, the reset is synchronized to the clockage here. On the second clock, you hit synchronized to the clock here. This is to avoid any metastability. Then the reset is deasserted to all the functional blocks in your register. This is to avoid any reset removal issues. So let us now see what is a recovery and a removal check. A recovery and a removal check is basically a set up and hold for your reset signal. So a recovery check ensures that the deasserted reset signal allows the clock signal to take control of the output at the desired clockedge. For this, the reset signal must be stable at least the recovery time before the active clockage and removal time after the clockage. This can be modeled similar as a setup check with the difference of it being single sided synchronous checks only. Coming to the last slide, we'll discuss briefly what is clog getting and its needs. Clog getting is basically a common technique used to reduce clock power by setting off clock to modules. So here you have an enable signal and a clock signal. When the enable signal is high, there's a clock going into the flip flops and when the enable signal is low, the clock is gated to all your modules. So there are specific checks in STA that needs to be done for clog getting. We will not discuss those in details in this course. But cloggeting is one of the techniques that is used to reduce dynamic power. Thank you.