Physical design interview questions

1. Introduction: Hello, everyone. Welcome to the physical design interview questions. Today we'll be covering some of the basic interview questions that are asked in a physical design interview. Let us begin. Before we start the course, let us look at some of the course requirements. You need to have a basic physical design background, some ACC flow knowledge, and some design basics would be helpful. Coming to the course structure, the course is structured in five different sections. In the first section, I will be covering PD flow and interview questions. In the second section, I will be covering floor planning and placement interview questions. In the third chapter, I'll be covering the clock synthesis and routing interview questions. In the fourth chapter, I'll be covering setup and hold interview questions. In the last chapter, I have additional section on PD interview questions. Coming to the course objectives, the course is to help students who currently have basic skills in physical design to quickly ramp up for an interview. If you have been following my LinkedIn profile, I have been regularly posting a daily interview questions to help cover broad range of concepts. So let us not waste any time and begin the learning journey. 2. Physical design flow interview questions : Hello, everyone. Welcome to the Chapter one of the series. Today I'll be covering the physical design flow interview questions. Let us begin. So the first question is, what are the different stages in a PD flow? So it is very important to know how the PD flow works. So the first stage is you import your design, and then you floor plan, then you take it through placement, and then you have the clocks in such a stage, then you route the design, then you sign off. I'll be discussing about each of the stage in detail in the next section. What is the Import design stage? It is the very first stage in the physical design. In the synthesis process, the RTL code is converted into a Netlist. In this Import design stage, all the input files are read by the tool. By using this information, the design process will start. The second stage in a physical design flow is floor planning. What is floor planning? The floor planning is the process of determining the macro placement. You have the different macros. You need to decide how you want to place these macros. Then there are power grids and IO placements. The IOs needs to be placed in the correct area. Floor planning is basically a process of placing the blocks, macros in the chip core area, thereby determining the rooting areas between them. It determines the size of the die. When we start the design process, usually at an architecture stage, a die size is given. It's very important we stick to the die size. It also creates wire tracks for placements of standard cells. It creates Power straps and specifies the pin connection. It also determines the IO, pin, pad, and placement information. Coming to the next stage, we come to placement. Placement is basically the process of automatically assigning correct position to the standard cells on the chip. There are two different types of placing. One is global placement. The standard cells are placed inside roughly, and then there is detailed placement in which the standard cells will place in site rows, also called legalized placement. In placement stage, we check the congestion value by the GRC map. Okay. Coming to the next stage, it is the clock tree synthesis. In this stage, we build the clock tree by using inverters and buffers. In the chip, clock signal is essential to all the flip flops. To give the clock signals from the source, we build the clock tree. In clock try synthesis, it is important is the process of balancing the clocks queue and to minimize the insertion delay in order to meet the timing and power. Coming to the last two steps, the last two steps are routing and sign off. Before routing, the connection between macro standard cells, clock, IOPort or logical connections. In this stage, we connect all the cells physically with the metal strap. Routing is divided basically into two parts. One is the global routing and second is the detailed routing. The global routing will tell for which signal which metal layer is used. In detailed routing, the physical connections are done. After the routing stage, we come to the sine of stage. The physical layout of the chip is completed in the sine of stage. In Sine of stage, all the tests are done to check the quality and performance of the layout before tapeout. This gives a brief overview of the different stages in your physical design flow. In the coming chapters, I'll be discussing in detail on these steps. Thank you. 3. Floorplanning and placement interview questions : So coming to the Chapter two of the series, we will be discussing about some of the floor planning and floor planning interview questions. Let us begin. To the first question, what is floor planning? It is the very first stage of the physical design. The quality of the floor plan will design the total chip performance. The floor plan is a process of determining the macro placements, the IOPOd placements, and it is the process of placing blocks macros in the chip core area, thereby determining the rooting areas between them. It determines the size of the die and creates wire tracks for placement of standard cells. So there are some of the important terminologies related to floor planning. What is a macro? These are special memory elements used to store the data efficiently. Also they don't occupy much space on the chip compared to these memory cells. These are called macros. There are two types of macros. One is a hard macro. A hard macro is basically the circuit is fixed and we don't know which type of gates that are used inside. We only have the timing information and not the functional information. Then it's called a hard macro. Then there is a soft macro. The macro, circuit is not fixed. We know which type of gates are going to be used inside. We know the timing information and also the functional information. And then we have the core. Core is the inner block which contains all the standard cells and the macros. Then at the outer surface, we have the D. It is the block around the core, which contains all the iopods. So the next question is, what are the different types of load planning techniques? There are three different types. One is the abutted technique and the second is the non abated and third is the mixed technique. What is the difference? In the abetted technique, when the chip is divided into blocks in abetted design, there is no gap between the blocks. The second is the non abetted technique. In this design, there is gap between the blocks. The connection between the blocks are done through routing nets. And the third is mixed, which is basically a mix of both abated and non abated design. Coming to the next question, what are the input files for your floor planning? You need your Net list, you need the standard delay constraints. You need the logical library information, the physical library information. You need the technology file, and then the TLN TDF files. Coming to the next question, what are the steps in floor planning? There are two main steps. One is the giving the aspect ratio, and then you have the core utilization. In giving the aspect ratio, aspect ratio will decide the size and shape of the chip. It is the ratio between the vertical routing resources to the horizontal routing resources or ratio of height versus the width. If the aspect ratio is one, that means the height and width of the chip is same. If the aspect ratio is 0.5, that means the width is twice the time of the height. Aspect ratio is basically height divided by width. The second is the core utilization. The core utilization will define the areas occupied by the standard cells macros, other cells. If the core utilization is 0.7, that means 70% of the core area is used for placing the standard cells macros, other cells. The remaining 30% is used for routing. What are the main steps in floor planning? The two main steps are placing the macros inside the core, cut the rows on macros. The main step in floor planning is placing the macros inside the core. After giving of aspect ratio and utilization factor of the chip, the size and shape was created. All the standard cells and macros are placed on the outer side of the chip. In this floor plan stage, we have to place the macros by some guidelines like fly line analysis, port communication, macro grouping, et cetera. Cut the rows on macros. In the floor plan stage, rows are created inside the core to place the standard cells. When we place the macros inside the chip, the rose will overlap the macros. We need to cut rows on the macros. What are the other steps in floor planning? Insert physical cells. Inserting physical cells like tap cells, endcap cells, filler cells, et cetera. These cells will protect the chips from faults. Then you have the Ioplacement. Iopads are placed at the boundaries in block level. These opins are placed at the input and output side of the block to interact with the other blocks and transfer signals. After that logical cell placement block is created in the die area to prevent the logical cell placement. The di area is only for the Iopins. Creating blockage. Placement blockage is applied in the floor plan stage to prevent standard cell placements. If we don't apply the placement blockage, there is a chance to overlap the standard cells on macros. We applied this at the macro area so that there is no chance to overlap standard cells on macros. So the next question is what is power planning? Power planning is basically used to equally distribute power to the cells, be it macros, standard cells or other cells. Normal connection will not distribute the power equally throughout the chip. So we choose special power design to carry power throughout the chip equally. In this step, there are three levels of power distribution. You have the rings, you have the straps and you have the rails. The rings are placed around the chip which carry the VDDN VSS. Straps. It is difficult to transfer power equally from edge of the chip to the center of the chip. So we place horizontal and vertical nets in the chip from rails to carry the power rails. The rails will connect the VDD and VSS to the standard cells. So the next question is how to decrease the air drop in a chip. So in power planning, we mainly concentrate on the airdrop and electro migration. In power planning, power is mostly transferred through power strap. So we have to decrease the a drop. Airdrop is caused by resistance. If resistance is more than a drop is more. Top metal layers will have resistance, so adrop will decrease. So we choose top metal layers. So we can decrease a drop by adding more straps or increasing the strap width. So another question that is commonly asked is, how do you fix the electromigration? The electro migration can be fixed by downsizing the driver. You can increase the metal width. You can add more vias or spread cells. Coming to the next part of the physical design flow, it is the placement. Dplacement is the process of placing the standard cells in rows created at the floor planning stage. The goal is to minimize the total area and interconnect cost. The quality is highly determined by the placement. What are the inputs to the placement stage? So you need the gate level net list. You need the floor plan design. You need the design libraries, design constraints and the technology file. This brings us to the end of the Chapter one of this series. In the Chapter two, we will be discussing more on the clock synthesis and routing. Thank you. 4. Clock tree synthesis and routing interview questions : Hello, everyone. Welcome to the Chapter three of the series. Today I'll be discussing the Clocktree synthesis and routing. Let us begin. So what is Clock tree synthesis? It is the process of inserting buffers and inverters along the clock path to balance the delay to all the clock inputs. Before Clockr synthesis, we treat clock as ideal. If we didn't build the clock, the skew and insertion delay will increase. This will affect the chip performance. To overcome this, we are constructing the clock tree by using the inverters and buffers. So the figure here shows the before clockrsynthesis, and the after clock try synthesis designs. So what are the main goals of Dcloctsynthesis? The main goals of the ccs synthesis is to balance the skew to minimize the insertion delay, minimize power dissipation and with the logical DRCs. What are the inputs required for your clotter synthesis? As we saw from the previous chapter, that Dclotrsynthesis happens after rear placement, you need a detailed placement database. You need a target for your latency and skew. So this is important that a target is specified and this is met in your Clockrsynthesis, and buffers or inverters are needed for building the clock tree, and then you need to complete the clock tree DRC. What are the checks that needs to be done before the Clockrsynthesis? You need to have a completed placement. You need to have a pre rooted power and ground nets. You need to have an acceptable congestion in your design. You need an estimated timing and the last thing is your HF NS. What is clock tree optimization? There are many techniques to optimize your clock tree. One is delay insertion. This will improve the whole time. Then there is buffering. This will improve the setup time. Then there is buffer relocation. This will reduce this and the insertion delay. And then we have the level adjustment. You can adjust the level of your clock pins to higher or lower. Then there is gate sizing. You can increase D or decrease D delay. To fix the max transition time, you add buffers and to fix the max capacitance, you decrease the net length. So coming to the next question, what is crosstow? It is the undesirable electrical interaction between two or more physical nets due to the cross capacitance between the two nets. So if you see here, you have two parallel running nets and there is associated with associated cross capacitance. This has an impact on the input going into the net here. So what are some of the crosstalk reducing techniques? You can increase the spacing between the aggressor and the victim nets. You can shield the nets, maintain the stable supply, increase the drive strength of the cell, layer jumping, victim net width increase, then the resistance decreases. Have a guard ring, and you can do cell sizing. Coming to the next step of your PD flow, it is routing. What are the steps in routing? You have global routing. It is done to provide instruction to detailed routing about where to route every net. It provides logical connection to all the cells. First, the design is divided into small blocks which is called G cell. Each cell will have a horizontal and vertical routing resources. Its aim is to reduce the total interconnect length and minimize the critical part delay by using by using the global routing, we can analyze the congestion. The second is the track assignment. It assigns each net to a specific track and lays down the actual metal tracks. Third step is detailed routing. Beside detailed routing, the connections are logical. In this theory, all the cells are physically connected. In this we specify the wire or interconnection in the channels specified by the global routing. Metal layer information of the interconnects are also specified here. The violations that are created in the track assignment are fixed in this stage. It doesn't root the entire chip at a time by dividing the chip into small block boxes, it will do the routing. The DRCs are fixed in detailed routing. The last step is the search and repair. It fixes the remaining DRC violations through multiple loops using progressive layer SPOC sizes. What are the goals of routing? The goals of routing are meeting the timing DRCs, minimizing the total wire length, minimizing the congestion hotspot, reduce the crosstalk, and minimize the number of vias. Thank you. 5. Setup and hold: Welcome back to the physical design interview question series. Today we'll be discussing about the setup and whole interview questions. Let us begin. So I assume by now most of you would have known what a setup time or a whole time is, but you're still not aware, I'll try to explain briefly. Setup time is a time before the clock edge by which the data to the flip flop has to be stable. And whole time is basically a time window after the clock edge, that the data has to be stable. Any violation between these two window will create a metastability. So let us uncover setup and whole concepts using this diagram here. Here you have a launching flop and a capturing flop. The data that is launched onto the launching flop goes through a combinational path and then reaches the capturing flop. Data has to reach before the setup time before the clock edge, and it has to be held stable for whole time after the clock edge. So what happens if a setup or whole violation occurs, the circuit goes into metastability. To avoid metastability, we need to make sure that the set up and whole times are always respected. Let us see an equation on how to calculate this setup and whole time. You have here you have the T clock to Q delay. This is the delay that is for the data to be launched from this flip flop, and then you have the propagation delay. The propagation delay is basically the time, it takes for the logic to propagate from this node to this node. You have the setup time, which needs to be basically honored for this particular flip flop or this particular circuit. You have the clock sku. Clock queue is basically the difference in the clock reaching this node to this node. Addition of all this should be less than the total time period. Let us see the equation now for the whole time. You have the clock to Q here and you have the propagation delay here. This has to be held stable for T hold plus TQ. This will give us an equation for so this gives us the equation for the setup slack. Setup slack is basically a T period minus T clock plus T plus D setup, minus T sq. A positive setup slack means the D circuit is not metastable. And this is a similar equation for the hold slack. Hold Slack is basically T clock plus T prop minus T hole plus T sq. If the hold slack is positive, that means there's still some margin available in the timing path. Let us see some of the interview questions based on this concept. So coming to an interview question, an interviewer may ask you, how do you tackle a setup violation in your circuit? This is based on your setup slack equation. The setup slack is basically T period minus T clock to Q plus, T prop plus T setup minus T sq. So a setup slack has to be positive to avoid metastability in your circuit. So how can this be done? This can either be done by increasing the T period, which is indirectly reducing the clock frequency that you time your circuit, or you have to either play around with these things. That is, decrease the clock to queue or decrease the propagation delay of your combinational path, reduce the setup time requirement of the capturing flop or increase the clocks queue between the capture and launch clocks. So these are the ways to tackle setup violation. So we saw in the last slide, some of the approaches to setup violation. Let us see in a real scenario how this is done. One of the approaches is to increase the drive strength of the datapath logic. A cell with better drive strength can charge the load capacitance quickly, resulting in the lesser propagation delay. You three prop reduces and your setup slack turns positive. Use data part cells with lesser threshold voltage. Usually in your cell library, there are the same cells with different threshold voltages. If you use cells with a lesser threshold voltage, it will have a lesser delay. Another approach is to restructure the data path. Based on the placement of data path cells, you can decide to either combine logic gates or split into multi state cell so that the propagation delay can be reduced. Another way is to play with the T clock. As a last resort, what you would probably do is time your design at a reduced frequency. So in the last two slides we saw how to tackle setup violation. Now we'll see how a hold violation can be tackled. A hold slack is basically T clock to Q plus T minus T hold minus T sq. To have a positive hold slack, you can increase the clock to Q delay of the launching flop, decrease the holding requirement, decrease the clock squeue between the capturing clock and the launching flop or increase the propagation delay. So we will see some of the examples on how to do this in the real world scenario. As we saw, we need to increase the propagation delay for to fix a hold violation. What do you do? You basically insert delay elements. This is the simplest that you can do. Two remove hold violations. Another way is reduce drive strength of the data path. Replace the cell with a similar cell of less drive strength. This will increase the propagation delay of the cell. The other approach is, as we saw in setup, we use cells with lower threshold voltages. For hold violations, we need to use cells with higher threshold voltages so that the propagation delay increases. Thank you. Another common interview question is, what is false path in your design? False paths are basically paths that are not timed in your STA. This may not be time for different reasons. One of the reasons may be that path is not possible architecturally. For example, if you take a max, here you have a select which is selecting the max and which is also input for Mx one. When select is zero, this path is not at all possible architecturally. So you can set a false path on this design. Another interview question that is asked is usually on the setup and whole time. For that, you need to remember the setup slack and D hold slack equation. So if the setup slack and hold slack is positive, that means there is no setup or hole violation. From the figure above, the T period is 10 nanoseconds. Clock to Q is two, T prop max is four, T setup is one and TQ is one. If you calculate here, the setup slack comes out two plus four nanosecond. There is no setup violation. Similarly, for the whole slack, you have clock to Q, TPp T hold, and TQ. So the whole slack is also positive. This circuit is timing clean. This brings us to the end of part one of the digital design log interview questions. Thank you for your time. 6. Additional PD interview questions : Hello, everyone. Welcome to this extra chapter on the physical design interview question series. Today I'll be taking you through some of the common interview questions. Let us begin. The first question is what are power getting cells? The power getting cells are used to avoid static power dissipation. The power getting cells are power switches, level shifters, retention registers, isolation cells, and power controllers. The second question is how to reduce latch up problem. The early SMS process suffered a reliability concern that became known as latch up. It resulted in circuits either malfunctioning or consuming excessive power or could be either inherent in the design or triggered by voltage spikes on IO pads that could forward BSP injunctions that were connected to. To reduce the latch up problem, you can increase the spacing between the PL and NVL increase the well substrate doping concentration or use ground rings around the device. Another common question that is asked is why is nine gate preferred over an gate? If you look at it, from a device perspective, at a transistor level, the mobility of electrons is normally three times that of holes. A nine gate is faster and has less leakage compared to an git, so it is preferred. So the next question is what are isolation and retention cells? The isolation cells are special cells required to interface between blocks which are set down and always on. It is necessary to isolate floating power inputs. Similarly, retention cells are special flops with multiple power supply. When the design block is switched off for sleep, more data in all flip flops contain desired states to retain. For this ten in flops must be used. In the diagram here, if you see when there is a power down and an isolation happening, you have an isolation cell here, which isolates this particular logic from this particular logic here. The next question is, what are the different types of cells that are used? So we have tap cells. These are used to avoid latch up problems. You have en cap cells. These are placed at the edges to avoid cell damage at the end of the row. We have decapscells. These are placed between power and ground rail to avoid ad rob. We have filler cells. These are used to connect gaps between the cells. We have ICG cells. These are used for cloggting. We have PAD cells to interface with the outside device IPTer clock pins are connected to PAD cells. Then finally, we have the Jax cells. These are used to check the Io connectivity. The next question is what is the difference between a hierarchical design and a flat design? Hierarchical design has blocks and sub blocks in a hierarchy and flat design has no sub blocks. It has only leaf cells. Hierarchical design takes more time to run and flat design takes lesser time to run. What are the types of blockages? We have hard blockage. It doesn't allow inverters, buffers and standard cells. We have soft blockage. It allows only inverters and buffers and block standard cells, and we have partial blockage. It allows both buffer and standard cells in a percentage value. The next question is what is congestion and how to fix them. When the available tracks are less than the required traps, this effect will occur. That is the congestion will occur. When the signals are more than the tracks, then congestion will occur. There are different ways to fix them. One is congestion driven placement. We can adjust the cell density in congested area because the high cell density causes congestion, use proper blockage, modify the floor plan of the design. The next common question is what is temperature inversion? At higher Samos technologies, cell delays increase when temperature increases. But when you are in the lower technologies that is below 65 nanometer, cell delays have an inverse proportion to temperature. This is called temperature inversion. The next question that is used is, how can you reduce dynamic power? You can reduce dynamic power by reducing the power supply voltage, reduce voltage swing in all the nodes, reduce the switching probability or reduce the load capacitance. Coming to the next question, what is scan chain reordering? Scan chain reordering is a process of reconnecting the can change in the design to optimize for routing. By reordering this chain connection, it improves timing and congestion. The next question is in rec to wrec path, if you have a setup problem, where will you insert the buffer? We can insert the buffer near the launch flop. This will decrease the transition time, hence decreasing the wire delay. Therefore, the overall delay and the arrival time will decrease, which will help the setup violation. Next question is, what is metal slotting? Metal slotting is a technique for avoiding problem like metal lift often metal erosion. What are the power dissipation components? There are three power dissipation components. One is the dynamic power consumption, other is the static power consumption and the last one is the short circuit power consumption. Dynamic power consumption occurs when signal goes through a sema circuit change. There is a logic state change by discharging of node capacitor. Static or leakage power consumption is power consumed by sub threshold currents or by reverse bias diodes in the semos transistor. Short circuit power consumption occurs during switching on both the mos and primose transistor in the circuits, and they conduct simultaneously for a short amount of time. This brings us to the end of this chapter. Thank you.