Digital RTL design and verilog interview questions

1. Introduction: Hello, everyone. Welcome to the digital RTL Design and Verilog interview question series. My name is Karen Basker and I'm working in the VLSI industry as a principal engineer for more than ten years now. This is the part one of the series. Today I'll be covering some of the basic interview questions that are asked in a digital RTL design interview. Before you start the course, let us look at some of the course requirement. You should have a basic digital design background, some basic Verilog knowledge, and some logic design basics will be helpful. Let us look at the course structure. As I mentioned earlier, this is an introduction series to the digital design and it is suitable for new students and professionals looking to get into the VLSI industry. If you're already an experienced designer, this course may be helpful to brush up your skills before an interview. Coming to the core structure, I will take you through some of the common interview questions that are asked on logic gates and encoding on synthesizable very lock code and questions and set up and hold interview questions. Coming to the course objectives, the course is to help students currently having basic skills in Verilog or digital design to quickly ramp up for an interview. I have been doing the same with my LinkedIn profile trying to post regular interview questions to help cover broad range of concepts. So let us not waste any time and begin the learning journey. Thank you. 2. Logic gates and encoding: Hello, everyone. Coming to the first chapter of this series, we will be discussing about the logic gates and codes. Let us begin. Coming to the first question and one of the common questions that are asked for freshers who are joining the industry is implement logic gates using two to one marks. So here, I have a implementation for an end gate. For an Ad gate, you have the X and Y, the X is connected to the select line and Y is connected to the select one. When x is zero, zero is always selected and when X is one, Y is selected. This is another representation of doing the same thing. Second question is on the nargt. How do we do an RgtUsing a two to one max? Here, we basically connect T X to the select line and Y bar to the zero input. When X is one, always zero is selected. That is the Nargt here. When a is one, always is zero, and when X is one, Ybr is selected. Coming to the Nand gate, it's a similar logic here. So when X is zero, always, one is selected. So where is NAD here, there's no h here, but when X is one, Y bar is selected. So you can probably put a table and see how this implementation matches. These are some of the other gates. For instance, here we have XRgate. For an XRgate you need to connect X to the select line and Y to zero output and Y bar to the one output. For instance, when X is zero and Y is zero, z is zero, zero, zero is zero. When X is zero and Y is one, so when X is zero and Y is one, is one. That is the X argate here. A similar representation for X n, but here, Y and Y bar is reversed. Coming to the not gate here, you basically have an X here. The select line is connected to the input, and you will get the inverted output on Z. When X is zero, you have one getting selected onto Z, and when X is one, zero is getting selected. And this is an gate. So when X is zero and Y is zero, z is zero when X is one and Y is one, one is selected, and when X is one, always one is selected. This forms the basic implementation of the universal gate using two to one marks. The second common question that is asked is, build a four to one mark using it, two to one max. This is a simple representation of four is to one mark using it, two to one x. You have the four inputs here and one output here. The two select lines, select zero is connected to the first stage of your max the select one is connected to the second stage of your max. You can work this out by writing your routable. The third question on logic gates is given only two XOR gates, one must function as a buffer and the other as an inverter. So how do we do that? So you have an XR and you have two inputs A and B. So for a buffer, the B input is selected to zero. So whatever is the value on A is held for a time and transferred onto orput Y. For an inverter, you have B as one and whatever is there on the input A is inverted onto the output Y. A third common question that is asked is, what is gray code and where is it used? To understand the difference between the binary code and gray code, let us understand how the representation is. So you see the decimal number 0-1, the binary and gray have the similar representation. But for decimal two, the representation for binary zero, zero, one, zero, but for representation of gray code changes here. The whole concept of gray code is there's a single bit change on every decimal change. From decimal two to three, there's a bit change here for decimal three to four, there is a bit change here. So when you take all the decimal 15 representation, you have only a single bit change between the decimal numbers. In the next slide, we will try to understand the applications. So where is gray code used? This is mainly used in clock domain crossing. Basically, when you have two clock domains that are asynchronous to each other, when we try to synchronize the binary count from one clock domain to another, if every bit is changing, this creates a problem. In clock domain crossing, usually, gray coding is used instead of binary encoding. Another important thing is it consumes lesser power as there are lesser bit transition. Also an asynchronous 54 design, gray code pointers are used instead of binary pointer because they have to cross the clock domain. Question four another common question that freshers is what is once complemented, two's complement. For the once complement, you basically invert all the bits in your bitstream. For instance, the once complement of 110, zero, one, zero is 001101. The twos complement is basically done by adding one to the one compliment. So what is the difference? In one compliment, zero has two different representation. That is a minus zero and a plus zero. But in two's compliment, zero has only one representation. Zero is always considered as a positive. And where is this once compliment and two's complement used? This is mainly used for signed binary numbers. It is used for signed binary addition and subtraction. Thank you. 3. Synthesizable verilog: Welcome to the second chapter of the digital design interview series. So in this chapter, we'll be discussing about the synthesizable Verilog code. Verilog is a hardware description language, and there are a lot of nuances too with syntax. So you need to be careful on how you code your Verilog. Let us see some of the basic synthesizable Verilog code. Coming to question one, the interviewer may ask you to write a Verilog code for a simple deflip flop. So a simple D flip flop is basically you have a D input, you have a clock and Q output. In wed log, you have always at block. This is called the sensitivity list. So when the sensitivity list, value in sensitivity list changes, the code is executed below. So the the D is slashed down to the Q when a positive edge of the clock occurs. So here you have your D input and you have a clock here. So on the rising edge of the clock, the D input is flopped onto the key output. The second question is, write a very lock code for a D flop bit, asynchronous reset. So here, it is quite similar to what we wrote before. You have the sensitivity list. Now here in the sensitivity list, you have also the posit of reset coming in. So if you have a reset, Q should be coming to a value of settling to a value of zero, L Q should lash the value of D. So here you have a clock, D and Q. So on reset here, the value of Q is pull to zero. But here on the clock heage here, the value of D is sampled onto value of Q. The third question is to write a code for defliplop with G it clock. So here you have a wired Gated clock, which is basically an end of enable and clock. So always on passage of gated lock, that is what is going to the flip flop. Q is lashed onto D. What happens here is the clock is basically gated. So when you enable a zero, there is no clock. The gated clock is zero. And when on the gated clock edge, Q is sampled onto the D output. Sorry, the D is sampled onto the Q output. So this is another variation of the deflplo called the data naval deflp flop. Basically, the code for this is Always on paste of the clock, if enable is one, D should be latched onto the Q. How is this synthesize? You have a x here, you have a D input, and you have a Q input. When enable is zero, the data is held to the previous value. When able is one, the data is latched onto the Q output. Let us see the waveform here. When the enable is zero, the is held stable. It is not changing with respect to the value of D. But when enable is one on the posit of the clock, the value of D is captured onto the Q output. The next question is on a latch implementation. You may be asked to basically demonstrate how latch works and write a synthesizable code for it. So here you have a sensitivity list consists of Q and enable. When enable is one, Q D is last down to Q. So when enable is one, the value of Q is changing here and it is kept constant when enable is zero and when enable is put high again, the value changes here. The next question is on a two to one MX implementation. There are various ways to write a two to one max. A simplest way is using a ternary operator. What is a ternary operator? Ternary operator is a question mark symbol here. Basically, when select is one, when select is zero, A is selected. When select is one, B is selected on two, T. This is basically a MX implementation. The MX can also be implemented using a K statement, like the one here. You have the sensitivity list here for A, B or select line. And you have a case select that is when select is one, you have one selected. I select is a selected, when you select is zero or default, you have B selected. So the last synthesizable code that I'm going to show today is the three input, priority, and code in marks. Here you have three signals AB and C, and you have a select line which is of two bits. If select is zero, zero, Q gets selected to A. If select is 01, Q gets selected to B, L, Q gets selected to C. Here you see in the wave form. When select is zero, zero, the value of Q is pull two value of A. When 01, it changes to value of B. When there is value of 11, the cube basically gets selected to the C value. This brings us to the end of the synthesizable lock code chapter. In the next chapter, you will see a bit more on set up and whole questions. Thank you. 4. Setup and hold: Welcome to the third chapter of the digital Design interview series. So in this chapter, I'll be discussing about the setup and whole interview questions. So you have already attended a digital design interview, you would have probably known that setup and hold is usually one of the questions that is asked in a digital design interview. Let us try to uncover the concepts. I assume by now most of you would have known what a setup time or a whole time is, but you're still not aware, I'll try to explain briefly. Setup time is a time before the clock edge by which the data to the flip flop has to be stable. And whole time is basically a time window after the clock edge, that the data has to be stable. Any violation between these two window will create a metastability. Let us uncover setup and whole concepts using this diagram here. So here you have a launching flop and a capturing flop. The data that is launched onto the launching flop goes through a combinational path and then reaches the capturing flop. Data has to reach before the setup time before the clockedge it has to be held stable for whole time after the clock edge. What happens if a setup or whole violation occurs, the circuit goes into metastability. To avoid metastability, we need to make sure that the setup and whole times are always respected. Let us see an equation on how to calculate the setup and whole time. You have here you have the T clock to Q delay. This is the delay that is for the data to be launched from this flip flop, and then you have the propagation delay. The propagation delay is basically the time, it takes for the logic to propagate from this node to this node. You have the setup time, which needs to be basically honored for this particular flip flop or this particular circuit. You have the clock sku. Clock queue is basically the difference in the clock reaching this node to this node. Addition of all this should be less than the total time period. Let us see the equation now for the whole time. You have the clocked Q here and you have the propagation delay here. This has to be held stable for T hold plus T sq. This will give us an equation for so this gives us the equation for the setup slack. Setup slack is basically a T period minus T clock plus T plus D setup, minus T sq. A positive setup slack means the D circuit is not metastable. And this is a similar equation for the hold slack. Hold slack is basically T clock plus T prop minus T hole plus T sq. If the hold slack is positive, that means there's still some margin available in the timing path. Let us see some of the interview questions based on this concept. So coming to an interview question, an interviewer may ask you, how do you tackle a setup violation in your circuit? This is based on your setup slack equation. The setup slack is basically T period minus T clock to Q plus, T prop plus T setup minus T sq. So a setup slack has to be positive to avoid metastability in your circuit. So how can this be done? This can either be done by increasing the T period, which is indirectly reducing the clock frequency that you time your circuit, or you have to either play around with these things. That is, decrease the clock to queue or decrease the propagation delay of your combinational path, reduce the setup time requirement of the capturing flow up or increase the clocks cue between the capture and launch clocks. So these are the ways to tackle setup violation. So we saw in the last slide, some of the approaches to tackle setup violation. Let us see in a real scenario how this is done. So one of the approaches to increase the drive strength of the data path logic. A cell with better drive strength can charge the load capacitance quickly, resulting in the lesser propagation delay. So your three prop reduces and your setup slack turns positive. Use data part cells with lesser threshold voltage. Usually in your cell library, there are the same cells with different threshold voltages. So if you use cells with a lesser threshold voltage, it will have a lesser delay. Another approach is to restructure the data path. Based on the placement of data path cells, you can decide to either combine logic gates or split into multi state cell so that the propagation delay can be reduced. Another way is to play with the T clock. As a last resort, what you would probably do is time your design at a reduced frequency. So in the last two slides we saw how to tackle setup violation. Now we will see how a hold violation can be tackled. A hold slack is basically T clock to Q plus T minus T hold minus T s. So to have a positive hold slack, you can increase the clock to Que delay of the launching flop, decrease the holding requirement, decrease the clock skeu between the capturing clock and the launching flop or increase the propagation delay. So we will see some of the examples on how to do this in the real world scenario. As we saw, we need to increase the propagation delay for to fix a hold violation. What do you do? You basically insert delay elements. This is the simplest that you can do to remove hold violations. Another way is reduce drive strength of the data path. Replace the cell with a similar cell of less drive strength. This will increase the propagation delay of the cell. And the other approach is, as we saw in setup, we use cells with lower threshold voltages. For hold violations, we need to use cells with higher threshold voltages so that your propagation delay increases. Thank you. Another common interview question is, what is false path in your design? False paths are basically paths that are not timed in your STA. This may not be time for different reasons. One of the reasons may be that path is not possible architecturally. For example, if you take a max, here you have a select which is selecting the max and which is also input for Mx one. When select is zero, this path is not at all possible architecturally. You can set a false path on this design. Another interview question that is asked is usually on the setup and hold time. For that, you need to remember the setup slack and D hold slack equation. So if the setup slack and hold slack is positive, that means there is no setup or whole violation. From the figure above, the T period is 10 nanoseconds. Clock to Q is two, T prop max is four, T setup is one and TQ is one. If you calculate here, the setup slack comes out two plus four nanosecond. There is no setup violation. Similarly, for the whole slack, you have clock to Q, T prop, T hold, and Ts. So the whole slack is also positive. This circuit is timing clean. This brings us to the end of part one of the digital design and log interview questions. Thank you for your time.