Clock domain crossing interview question

1. Introduction: Hello, everyone. Welcome to the clock Domain crossing interview questions. This is the Part one of the series, and today I'll be covering some of the basic interview questions that are asked in a digital RTL design interview related to clock domain crossing. Let us begin. Before we start the course, let us look at some of the course requirements. You need to have some basic digital design background, some clock domain crossing knowledge, and some logic design basics will be helpful. Coming to the course structure, an introductory series to clock domain crossing and is suitable for both new students who are trying to get into the industry and for professionals who are looking to quickly ramp up for an interview. The course is divided into three main sections. The first section is addressing interview questions related to clock domain crossing issues. The second section is addressing interview questions relating to MTBF, two flip flop synchronizer and flop synchronizer. The third section is addressing related to synchronizers with feedback, Mx recirculation and they commonly ask divide by 32, three, and four circuits. Coming to the course objectives, the course is to help students who are starting their journey into digital domain to understand some of the clock domain crossing concepts and to help them ramp up quickly for the interview. If you're already following me on LinkedIn, I've been regularly publishing a daily interview questions related to digital design to help cover broad range of concepts. So let us not waste any time and begin the learning journey. Thank you. 2. Clock domain crossing issues : Welcome to the Chapter one of the series. Today I'll be discussing some of the common interview questions asked in a clock domain crossing related to the clock domain crossing issues. The first question that you might be asked in an interview is, what are the basic issues when a data crosses from one clock domain to another clock domain. You have a data here, which is crossing a flip flop from a different clock domain to a flip flop in another clock domain. There are three major issues that we face. First is metastability. Second is data loss, and third is data incoherency. We'll discuss these in detail in the coming slides. Coming to the second question and one of the common question that is asked, what is metastability? Here you have two clock domains. A data is crossing from clock domain C one to C two. If a transition of signal A happens very close to recapturing clock domain, the data from the second flip flop may become metastable. So what does it mean? The data can either go to a logic one or to a logic zero, and the output is unstable for a long time. What does this mean? That means there is a high current flow, which is not an ideal situation. And on the fanout, the output can settle to either a logic one or a logic zero, which means the functionality of the circuit is compromised. So what happens when there is meta stability? If the unstable data is fed to several other places in the design, it may lead to high current flow and even cheap burnout. Different fanout cones may result in different values of signals that we just saw and may cause the design to enter into a unknown functional state leading to functional issues. The destination domain output may settle down to a new value or may return to old value. Or the propagation delay could be high leading to timing issues. The second problem that we saw with clock domain crossing is basically data loss. So here we see two cases where a different set of input data may cause a data bit to get lost. Here C one is twice as fast as C two and there is no phase difference. The data on A is correctly captured on the destination clock domain in this case. In the case here, because C one is twice as fast as C two, a pulse here is basically lost in destination domain B. The third issue that we saw with clock domain crossing is data incoherency. What does this mean? Consider a case when multiple signals are being transferred from one clock domain to another clock domain. If all the signals are changing simultaneously and the source and destination clock arrive close to each other. This may result in invalid value of combinations in the destination side. We say the data coherency is lost. If you see here, we have a bus of bit to bit wide. Here, value zero, zero is correctly captured in the destination domain. But when there is a transition 00-11, you see due to metastability, the Y is going to 10, which is invalid and later it settled down to 11. This may cause functional issues in your circuit. 3. MTBF and synchoronizer questions : Welcome to Chapter two of the series. In the last chapter, we saw some of the problems that we face when we cross clock domains. In this chapter, we will see some of the concepts that are used to remove clock domain crossing issues and some of the basic synchronizers. One of the most common synchronizers that is used to resolve lock domain crossing is two flip flop synchronizer. So here, a signal from a clock domain A clock is going into clock domain, B clock. So what the basic concept of a two flip synchronizer is, even if the first stage of the second synchronizer goes metastable, it can be captured correctly in the second stage. If you see here, you have the signal ad at, which is basically the signal that is going from clock Domain one to clock Domain two. So in the first clock, the BQ, the beat one goes metastable. But since we have two flip flop synchronizer, the second the second flip flop is able to capture the data correctly. In the last slide, we saw how a flip flop synchronizer can be used to resolve metastability. But is two flip flop enough or do we need to have more than two flip flops at the destination domain? For this, what is important is to calculate what is called MTBF. MTBF is basically meantime before failure. It is calculated basically with equation, which is one by F clock into F data into X. For most applications, it is important to run calculation of MTBF for any signal crossing a CDC boundary. A failure in this sense means a signal that is passing through a synchronizer flip flow and continues to be metastaable one cycle later. When it's sampled in the second stage, synchronizer flip flop. Since this signal did not settle down to a known value after one clock cycle, the signal could still be metastable when sampled and passed to the receiving clock domain. This causes potential failure to the corresponding logic. When calculating MTBF, larger numbers are preferred over smaller numbers. Larger MTBF number indicate longer periods of time before potential failures. While smaller MTBF number indicate that metastable could happen more frequently. If you see here, if you have a higher F clock and a higher data changing frequency, that means your MTBF number is lower, which means the circuit can go metastable quickly. So my question from previous slide was, when is 23 flip flop synchronizers needed? For very high speed designs, the MTBF of a two flop synchronizer is too short. A third flip fob added will help to increase the MTBF to a satisfactory duration. Who decides this? This is usually determined by the architect of N design. Another common question that is asked is, do you need to synchronize the signal coming from the sending clock domain? The synchronization of signal from sending clock domain reduces the number of edges that can be sampled in the received clock domain. This effectively reduce the data change frequency in the MTBF equation. Hence increasingly time between the calculated failures. If you see here, the adat is basically changing because there is a combinational logic here. If this change happens very close to the destination domain, then it causes a failure. It's always a good idea to have this logic synchronized at the source before it's sent to the destination domain. 4. Other synchornizer questions : Hello, everyone. Welcome to the Chapter three of the series. In the last two chapters, we saw what are the issues that are faced in clock Domain crossing and how some of the issues can be resolved using a two stage flip flop and a three stage flip flop, and what MTBF is. In this chapter, we will try to dig deeper and understand different other synchronizers. The first question that you might be asked is, what should be the consideration that needs to be taken when you're synchronizing slow signals into fast clock domain? Usually synchronizing from slow domain to a fast domain is not a problem unless the faster clock is greater than one point times five times the frequency of this low clock. The fast destination clock will simply sample this low clock more than once. In these cases, the simple two fif flop synchronizer may suffice. So the next question is what is synchronizer with a feedback acknowledge? This is considered one of the safer approach for clock domain crossing. The source domain basically sends a signal to the destination clock domain through to flip flop synchronizer, and then passes the synchronization signal back to the source clock domain, through another two flip flop synchronizer as a freed back acknowledgment. The figure shows a waveform of the synchronizer, which is shown in the next slide. So this shows the wave form for the synchronization. Basically, the A data gets synchronized through a two flip flop synchronizer, and the data gets captured here on Bcter data after two edges of B clock. And then it is fed back to the AClock domain, and after two edges, the data is received out on the destination domain. This is considered a safer approach for synchronization, but there's a penalty in the number of clocks that is used for the domain crossing. So in Chapter one, we had seen a problem with the data incoherency. So this data incoherency can be basically resolved using x recirculation logic. Let me recap on the data incoherency here. So basically, you have the g zero and X one, which is transitioning here and crossing a domain. So the y zero and Y one, which is the domain crossed value is going into is going into invalid data here. So basically, y0y1 is now. 10 rather than 11 and it only gets captured here. How can this be resolved? This can be resolved using x recirculation logic, which is shown in the next slide. So the next question is why is x circulation synchronizer needed to resolve basically the data incoherency problems. You have the source domain here and a destination domain here. You have a bus of a zero A one, which needs to cross a domain to zero B one. What happens is a control enable signal is generated in source domain is synchronized in the destination domain using a multi flop synchronizer. The synchronized signal enable sync is then drives the select pin of the maxes thereby controlling the data transfer of all the bits of bus A. This way, individual bits of bus is not synchronized separately and hence, there is no data incoherency. However, it is important to ensure that when the control signal is active, the source, domain A zero and a one should be held constant. Another common question that is asked in the interview is the divided by circuits. Here we see a basic example of a divided by two circuit. A divide by two circuit can be arrived by connecting the car output of a deflip flock to the D input. You have the reference clock and the cube is basically divided by two clock. So what happens here is the Qbr is held for a complete cycle when the clock when you clock the deflip flop. So on every positive edge, the value the value changes, which will give you a divided by two circuit. Here you have a divided by four circuit. This is similar to the divided by two, but you have two deflip flops, and you are dividing this by the reference clock once here and dividing the reference clock again here. So your Qu will basically be a divided four version of your base clock. So let us come to the final circuit and most common asked in interview question is to basically arrive at a divide by three circuit. So this is a bit complex compared to the first two circuits that are shown. But, um, the basic approach here is pass the second flip flop output to one more flip flop, which is triggered as the negative edge of the clock. So you have the reference clock here. You have the negative edge clock here. And you make Ring of quarter and Q. This is required to achieve the divide by three 50% duty cycle. Let's see how this works in this wave from here. You have the reference clock here. Q zero is basically a divided by two version of the reference clock. Then you have Q which is basically a shifted version of the Q zero clock because you have a difl flop here, you have a shifted version of Q zero here. Q is basically captured in the negative edge of the diflp flop. You have a Q here. Now, what is done is basically an R of Q and Q. A Q and Q is R together to get a divided by three circuit. Thank you all for your time.