Systemverilog UVM interview questions - part2 | Kiran Bhaskar | Skillshare

Systemverilog UVM interview questions - part2

Kiran Bhaskar, Teacher

Systemverilog UVM interview questions - part2

Kiran Bhaskar, Teacher

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4 Lessons (20m)
    • 1. Introduction

    • 2. SV/UVM questions

    • 3. Digital verification/UVM questions

    • 4. Protocol/SV/UVM questions

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About This Class

System verilog UVM interview question series is an attempt to help students and professionals already having basic knowledge of the language and methodology to quickly ramp up for the interview . I have been posting daily interview questions on digital verification on my Linkedin profile .I have provided links to all the questions that i will be discussing in detail in this course .If you still have questions on the topics please feel free to comment on the respective question in the link below .

Day29:What is a UVM Heartbeat ??

Day28:What is the difference between a p_sequencer and m_sequencer?

Day27: What is the difference between late randomization vs Early randomization of sequences ?

Day26: What is the difference between rand and randc in systemverilog ?

Day25: Why is AHB burst not allowed to cross 1KB boundary? Can we have more than 1KB space allocated to each slave?

Day24: What is virtual sequence and virtual sequencer in UVM?

Day23:What is mailbox and queue in systemverilog ? what is the difference between them?

Day22:What is blocking and nonblocking assigment in verilog/system verilog and why is only non blocking assignment are used in UVM driver?

Day21:What is callback in Systemverilog/UVM?

Day20: Difference between code coverage and  functional coverage ?

Day19:What is a virtual interface in SV/UVM and how is if different from a normal interface?

Day18:What is upcasting and downcasting in Systemverilog?

Day17: Difference between shallow copy (Copy) and deep copy (clone) in Systemverilog UVM?

Day16:What is the static component and dynamic component in UVM?

Day15: What is the difference between include and import in systemverilog ?

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Kiran Bhaskar



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1. Introduction: Hello, everyone. Welcome to the system will argue. Veum Interview series This is the part two of the series. My name is Karen Bhaskar, and I'm working in digital verification domain as principal engineer. For more than 10 years now, I have extensively worked with the system with Logan Devia methodology. Today I will be discussing over the common interview questions that students and professionals face when they're tender. Distal verification will say interview. So let us begin before we start the course. Let us look at some of the course requirements You need to have a basic knowledge off. Digital verification, some system very long anyway. Um, knowledge would be helpful if you're still a fresh. Sure, I'm looking toe. Get into the industry outside just you to take my system very long, UVM step by step course Before starting with the interview cities coming to the core structure, I'm going a broad range of interview questions not only on System Maryland UVM, but also on digital verification and some of the bus protocol questions that are commonly asked in an interview. If you're following Wellington Profile have been regularly publishing a daily interview question Siri's to help cover a broad range of concepts. The course objective here is to help students currently having basic skills in New Veum system very long or digital verification to Rampal quickly for an interview. So let us not waste any time and begin the learning journey. Thank you. 2. SV/UVM questions : Hello. Welcome to the system below. Give you interview Question Cities is the part of the city's Let's get started. Welcome to the question one of the part of the series and question 15 of the overall. What is the difference between including important system very long. These are basically used to include system very locked classes from different files in tow . Another file include is nothing but copying the contents of one filing to another. The compiler basically treat this US copying the whole contents into the file that you're including in import doesn't do any copying. He just makes the name visible for a particular class. For example, imagine you have a class air defined which you want to important Package X and package way . If you do include people basically copied E class in each of the package. But if you do an import, there will be only off one copy of Class A, which gets pointed to by the import coming toe. Question 16. What the study component and dynamic component in you, William. So as the name indicates, dynamic components are generated, they performed their tasks and their life span is finished at the end of a simulation cycle . On the other hand, started components are physical components result presentence d beginning and remain existed even after the end of the simulation. If you think about ah, you ve, um, system were locked based test bench. You need to designed to be active directory or dissimulation, so design or duty is a static component. All your class based cool only gets created during the simulation, so you want to send a package, create a class, you create a package, you send it on to your design. This these glasses have dynamic life lifetimes, meaning that the good Creator and they get destroyed by executing procedural court. So different desk and sick, different values to let us mention, Merman asked their dynamic. So coming to question 17 what is the difference between shallow copia and deep copy into stomach low give'em shallow copies, creating a new object and basically copping all the non static fields? What is non static fields? The fields that do not have A a difference. So a big, big, big copy off all the fielder performed the references copied, but their effort object is not therefore the original object and its clone refer to the same object. Deep Copy is creating a new object and then copying the non static fields of the current object to the new object. If the field is a value type, then a bit by bit copy off its fearless perform. If a field is a reference type than a new copy off the referred object is performed. The UVM clone matter is used for providing a deep copy of the object. The clone first basically creates new memory for the objects and then copies for each field off to the new object. Coming to question 18. What is up? Casting and don't casting in system Very low. Requesting is basically gusting to a super type. Why don't casting? It's got gusting to a subtype Up casting is always alone, but dont gusting in Walter type check and control class caste exception errors, For example. It is always legal to assign a child class tour bearing class, but it is never legal to directly assigned a super class tour subclass. Non casting is not legal in system very long come into question 19. What is a virtual interface and system where llegue Veum and how is it different from a normal interface. The interface is used to simplify the connection between the design and the test bench. So as instant as the interface can be instant stated, insert a class or a program block. We need a virtual interface. No, let us try to understand why the interface cannot be instance hated. Insert a class or a program block. This is because the interface is a started component and classes are dynamic nature. Because of this, it is not allowed to declare interface within classes, but it is a lotto refer or point to the interface au reum conflagration database is usedto sector and get D interface handle toady class hierarchy. Thank you. 3. Digital verification/UVM questions : I come back? This is the part two off the system would love. Give'em Interview Question Let us begin coming to Question 20 and this is a digital verification question. What is the difference between court coverage and functional coverage? This is commonly asked in most digital verification interview questions, and it is good to know about this. His boat, called Cooperation function coverage important well there to see Corcoran's gives information about how many lines are executed in your design. Functional coverage is something that is defined by your verification engineers uses redefined the coverage 0.40 functions to be covered in your design. This is completely under user control, So let us take an example. Let us say the design is supposed to verify three features A, B and C, and let's say the article quartered only feature A and feature B 70 test exercises feature A and feature B. You're court coverage will reach 100% but that doesn't mean the design is complete. So a functional coverage which basically courts for future seyval not be 100% and it will say the design for the verification is not complete. So does that mean functional, covered it. You functions over Regis 100 person, the the product is ready for sign off. No, this is because the functional coverage is something that a user courts or the verification engineer courts Sophie's incorrectly. According the functional coverage, it can lead to 100% functional coverage. So in verification domain, both functional coverage in court coverage is important. Hang their design needs to basically check for the very fire has to basically check woody coverage items coming to Question 21. What is a callback in system? Very low Give'em UVM, called Black Plus, provides a base class for implementing callbacks. These are typically hooks that are provided inside your verification components to make them more usable. Let us take any example. You have a driver developed and this driver is basically sending their transaction to your design. And let us assume the user wants to inject an error. So every AP provider will basically probably called back to your driver, saying inject at our this facility will change deep before it behavior. We talk the need for modifying the driver court. So Question 22 what is the blocking and non blocking assignment in very longer stumble along and buys only non docking assignments used in a driver. To understand this, you need to understand how the simulator operates. The simulator basically operates in four steps or for even cues. One is the previous time slot, the active Times Lord, a non blocking assignment and then the postman block. So the active do is rare. Most very low cord is scheduled, including the blocking US in Maine. The N B A. Region is where the ablation off Allegis off non blocking assignment takes place. So the problem is blocking. Assignments always suffer from a risk condition because all your very low quarters, most of your with low court is executed in the active stage but non blocking assignment. There is no such problem since the updated values assigned after the time step. So driver in your in your verification component will usually be using non blocking assignment to eliminate race condition. On the other hand, since monitors pursue and it is only sampling, the monitor should use blocking assignments. Coming to Question 23 what is a mailbox and Cuban system with the look? And what is the basic difference Accuser data structure, which is basically an ordered collection off homogeneous elements. It is basically liken, unpacked Harry Gross and shrinks at runtime that you can be bounded. That is, the number off interest limited are unbounded, that is, with unlimited entries and accuse can be used to access last in first or hard first in faster. So basically, as and when you want to dump something into a que you'll push our pop it in or out of the queue. So a mailbox and mail book is something which is built around the queue that uses, Says Summer. For to Control access. Millbrook has a before lamenting order. You basically use mailbox when there is a multiple threads reading and writing data. So if you have one thread, which is accessing the mailbox and you want to stop another trait to access this, you use the same before. So for single trade or single third process, there is no difference between a Q and A mailbox. So Question 24 what is the what you'll sequence and what Chelsea concerning UVM. A virtual sequence is a sequence which controls the stimulus generation. Using several sequences in UV um, architecture sequence and sequences are focused on point in the faces. For example, if you have an architectural where you have multiple masters, I would want to drive data partly or serially, on these different interfaces. So you will basically user what shall sequencer, which is basically a pointer to the actual sequencer in your environment about your sequence, basically runs on this bushel sequencer. 4. Protocol/SV/UVM questions : welcome to Part three of the system along UVM. Interview questions there to speaking this Question 25. And this is a protocol question. Twice he hits me. Bush not allowed to cross the one k boundary. And can we have more than one K B A locator to each slave? One Kilobyte is a smallest area offer. It has be sleeve that can occupy a memory map. If it hits be slave samples had sell X at the start of a Bush transaction, it knows it will be selected for a duration of the bust. Also a slave, which is not selected. The start with the burst will know that it will not become selected until a new buster started. Therefore, if a burst did cross a one K boundary, the access code stock the access that from a master could start accessing once labour the beginning and switch to another boundary, which would not happen. So in practice dismissed that master must always breaking burst that would otherwise caused the one K boundary and restart with their non sequential transfer. Question 26. What is the difference between Rand and Ranchi in system very log variables declared with Frankie work our standard random variables. That means their values are uniformly distributed over their range, but Ran sees a random sigh click variable. That means random musician values don't repeat a random value until every possible value has bean assign. So they're just taken example here I'm random using a package for five intervals, and this is basically a three big address address, one and others, too. One is defined as a language, and the other is different. Is that Ryan Siebert? So if you see here, the value tree is repeated for address one because it's a Randall big. But if you see there is no reputation here for the I don't see define address to Question 27 what is the difference between later and urbanization and hardly random ization off sequences, So sending a sequence item to our driver in wants four steps. You have to create the item. You have to start the item randomized euratom and then finished the item. The Strip three can award be interchange with Steptoe in Later, and a musician a sequence first cause D start item. Ray Dentals, the ill bred aeration, is granted from the sequencer and then just before signing the transaction toe. The sequence of our driver, the Randomizer is called. This has the advantage that D I comes up always randomized just in time and can use any feedback from other components just before sending the item to the driver. An alternate approaches to randomised the I come and then start the item in. Discuss the item. Get generator before it is necessary. This is referred to us earlier and immunization. Question 20 You. What is the difference between a P sequence Surrender M Sequencer Au reum sequence is an object with limited lifetime, unlike a sequence or a Red River, which are you beom company and their present throughout D two Malaysian Lifetime. If you need to access any members or handles from a distance heroically, the sequence would need the handle of the sequencer on which it is running M sequences and peak sequence. There are basically lady handles. M sequencer is basically a handle off the Type Williams Sequence airbase, which is always available by the 14 The UVM sequence, however toe acted the real sequencer on Mr Sequences running. You need to typecast D M C Questar toady riel sequencer, which is an area called E P sequencer. The sequencer is there type specific sequence pointer created by registering the sequence, too. The sequence of using the P sequencer Micro coming to question 29 and the last question in the series. What is it you Veum? Hard wheat heartbeats forwards away for the environment to ensure that there descendents are alive. A UVM heartbeat is associate with dead within specific objection. This is basically like a watchdog timer that you have in your design. The components that are registered for the heartbeat basically has a counter of the counter elapses. That means there's something wrong with your test bench or there is a hanging your test bench. And there is a way for your simulation toe end when the heartbeat time time is elapsed. This is one of the ways to find your simulation. Thank you.