System verilog UVM interview questions - part1 | Kiran Bhaskar | Skillshare

System verilog UVM interview questions - part1

Kiran Bhaskar, Teacher

System verilog UVM interview questions - part1

Kiran Bhaskar, Teacher

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4 Lessons (31m)
    • 1. Introduction

    • 2. Interview question on SV/UVM

    • 3. Interview question on protocols/SV/UVM

    • 4. Interview questions on GLS/SV/UVM

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About This Class

System verilog UVM interview question series is an attempt to help students and professionals already having basic knowledge of the language and methodology to quickly ramp up for the interview . I have been posting daily interview questions on digital verification on my Linkedin profile .I have provided links to all the questions that i will be discussing in detail in this course .If you still have questions on the topics please feel free to comment on the respective question in the link below .

Day14: What are the challenges in running a GLS?

Day13: what is gate level simulation (GLS) or netlist simulation ? Why is it necessary ?

Day12:How can sequence get exclusive access to a sequencer? what is the difference between grab and lock ?

Day11:What is the difference between SPI and UART?

Day10: Explain transaction level modelling in UVM?

Day9:What is the difference between AHB and APB protocol?

Day8:What is factory in UVM , why is it needed?

Day7: What are the different styles of fork and join in system verilog?

Day6 : what is the difference between SPI and I2C?

Day5 : What is the difference between APB and AHB protocol?

Day4: What is objection mechanism? How to finish a test in UVM?

Day3: What is the difference between new() and create() in UVM?

Day2:What is active agent and passive agent in UVM?

Day1: Why phasing is used? What are the different phases in uvm?

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Kiran Bhaskar



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Technology IT Security Verilog

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1. Introduction: Hello, everyone. Welcome to the system Very low. Gilliam interview question. Siri's My name is good in Bhaskar, and I'm working in the digital verification domain as a principal engineer. For more than 10 years now, I have extensively working the system very long and they were metrology. And today I will be discussing about the common interview questions that students and professionals face when the attended digital verification. We unless I interview before we start the course, I just look at some of the course requirements you need to have a basic knowledge off. Digital verification, some system very long anyway. Um, knowledge would be helpful if you're still a for sure, I'm looking toe. Get into the industry. I would suggest you to take my system very long, UVM step by step course before starting with the interview cities coming to the core structure, I'm going a broad range of entering questions not only on system of law Gov um, but also on digital verification and some of the bus protocol questions that are commonly asked in an interview. If you're following Wellington Profile have been regularly publishing a daily interview question Siri's to help cover a broad range of concepts. The course objective here is to help students currently having basic skills in New Veum system very long or digital verification to Rampal quickly for an interview. So let us not waste any time and begin the learning journey. Thank you. 2. Interview question on SV/UVM: Hello. Welcome back to the system ideologue. UVM interview question. This is the part one of the city's let's get started coming to the first question of the series and one of the common questions that was asked in the interviews. Why is facing used? What are the different faces in you, William? So you should know that every component in New Veum goes through a faking facing mechanism . There are three main faces that are executing the build connect under run phase. Defacing is used to basically control the behavior of this assimilation in a systematic way , The next light explains in detail on how the fizzy mechanism books, as we discussed in a large slide, each UVM component goes through the face implementation. So this slide we will try to understand what a UVM faces. So once they run matter discord, the UV en route component triggers and missions that you be on facing forces, the bill face executes in time zero. This basically builds all that expense components. The next faces the connect face where all the test bench components are connected together . It makes all the TL, um connections assigns all the handles to the distances Assis. Then we come to the run, face their own faces where the stimulus gets generated and simulation time advances. The bill face basically build and connect Face basically runs in time. Zero. The run faces again subdivided into different smaller phases. In the new movie Um, implementation, we will not. We will not goto this, but it is basically different implementation on the pre reset face configure face remain face main face and pushed Memphis. Then we come to some of the clean cleaner faces. So the cleanup faces used to extract results from the school world. Check whether the test case passes or fails based on some conditions. This may be, for example, if all packets sent down from an eternity master or received on an eternity sleep coming to the next second question and another common questionnaire. Disaster. What is an active agent and a passive agent? This is described in detail in the next life. So before we understand the syntax off A, you re imagine you will try to understand what are its components. So if you see the negative year, so you basically have a sequencer which produces data. The sequence of this connected to a driver through a special he'll import. The driver basically gets the data and transfers the data in do been level activity. So the sequence of driver interaction is at a transaction level, and their diver breaks the transaction into pain level activity. Want to your design and how is the data center? Were designed through the Watch Island office. And then there's the monitoring part, so your monitor keeps checking on your interface so basically receive digital. So you're converting your pain level activity again, back to a transaction you're monitoring on your design for any new transactions. Once the transaction is with you, it is basically written on two on analysis. Return through an analysis port on two D Project scoreboard or to any under he'll import, which is connected to this monitor. The agent until has other important information, like the active passive and past Dixon has Cottage. The active passive basically tells whether the agent is being usedto drive data, our only usedto monitor. So if it's an active agent, you will have the sequence of driver presenting the agent. If it's a passive Asian, do well only have the monitoring part of the Asian The agent also has mattered to basically disabled checks, so you can disable checks in your monitor or you can disabled coverage in your monitor. So all this has to be the usability quartered in your agent. So what is the difference between new and create new is one off the native constructs that existed even before UVM came into existence? This was a part of the system, very log language. And it's not give'em specific. When you create an object using new, the object never gets Resistol onto the factory. So when the object this when object has never registered onto the factory, it cannot be overdone. It the next light. I will discuss a bit more on how factories it's used to override company behavior and type behavior. In the last slide weed be discussed about the UVM freezing. So in this light, we're going to discuss another concept off UVM and what can still see you. Bm that is the factory. The factory, basically it's used in the bill face, so factory has to different types off over adoptions, so you can all right, any component in your environment using a type are using an instance so if you see the example here, you haven't a PB master driver that is being used. And when you basically use this in your dispense the epi be mustered driver gets replaced by a PB new master driver. So all the all the component which are using the A P B master driver type gets changed to the A p B new master driver type. So this is really helpful in developing reusable agents come into question for what is objection Methodism and how to finish testing new Veum in traditional dispensers. We have dollar finish after the quick step, right, he said. Configure and other data transfers their complete. Over in new beom, a new mechanism is used. This is called objection mechanism, basically what this objection mechanism do way. We saw that in one of the previous lights. Each component in New Veum goes through them facing mechanism. So every component also has an ability or every face has an ability to raise an objection. So assume there are 10 components in your E. William Dispense and each company into doing it ran face with raising objection, saying I'm starting a task and only stop dissemination after I complete a particular task. So only when all the 10 components in your movie, um, says I have completed my task. The simulation will come to an end. So this is a way for you, Veum no single nice D certification activity and to stop the test coming to the next question. And there's a protocol question that is commonly asked, What is the difference between an A P B and then the hits we protocol MPB protocol. It's used for connecting low banquet peripherals, while HB is useful connecting hired banquet peripherals. MPP is a non pipeline protocol and HB has some kind of pie planning in place. MPB is mainly proposed for connecting simple peripherals which is shown in the next slide. I showed them this late here You have an arm processor and you have a common in history bus . You have these higher bandwidth requirement preference connected onto the Hezb e bus. You have the on your program the DME and the high bandwidth extra interface connector on the HB. These require higher bandwidth and these are on H B. Then there are these preference like you are timer, keep our P O which are no banquet peripherals, and they do not require any kind off by planning requirement. So they are on a bridge which converts any hits. We brought a cold one, a BB protocol. 3. Interview question on protocols/SV/UVM : Hello. Welcome back to the park to off the system. Where? Long interview questions. Let us begin. Let's start depart. Two off two CDs with a critical question. What is the difference between I to CNN s p A protocol I to see? Use the stupids S d and s E l Well, SPL uses at least three prints. The mustard out slaving master inflatable. I'm S e k in terms off clocking I to see you. This few standard clocks 100 kilohertz, 400 kilohertz, etcetera. His spirit, on the other hand, can be used anywhere below 10 megahertz. In terms of application, I don't see it's cheaper to implement than S p A. We will see in detail in the next light on the basic differences. So as seen in the connection diagram here you have a mustardy ways and the slavery ways the master needs to talk to the sleeve. So how does this happen? You have a same clocking lying between I to see in the spear you have here is called a C L . And here also it's called a seal. The clock is connected between the master and the slave device and the data off in SP A is half duplex communication That means the mustard and sleep cannot talk to each other at the same time. But in SP, a point of view you have on my 30 ways blocking the slave Anyways, you have separate chip selects going to sleeve the slaves one will have a chip select one and slave who will have a chip sector. So when the what money master sends a frame on the most sip in the slave response on the miso pin So in the same frame you can have the slave respond duty master commands so SPS faster in dumps off in terms of speed But in terms of hard later it requires four wears and it is a big costly to implement. Okay, coming to question seven, this is a stomach low question. What are the different styles off work and join in system very long. So there are three starts off work and join firstly to understand for conjoined. What does it do? This is basically used to spawn multiple threats when running system Very look this bench we will see how these different flavors interact with each other in the next life So these are the 34 conjoined flavors that I discovered in the last light. So you have before conjoined. Basically this complete only when both off this is trains are complete. So here, What is the execution When the four can join of this happens, but A and B are displayed. Then you have working join any So this complete when anyone off the parents complete. So here he displaced a and it exits out of this fork and the B is never displayed and then it continues within except off instruction. Then you have the for conjoined None. So what happens is it will probably fork train A and train B and after five the simulation cycles is printer and after simulation cycles 10th simulation cycles bees, printer. And after this statement, assume if you had another display See here the displaced. He will also be printed after five simulation cycles, so it will not wait for completion off any three. So these are the three different variants off work and join question eight. This is a U B M question and the common concept it is used when using UV Um, what is factory newbie? Um, why is it needed and what has been a factor? Override. So the purpose of factory in UVM is to change the behavior for test bench without any change in court. The factory is basically like a look up table. When you create objects, you basically register. This objects with their factory. See this syntax? Here you have two agents which are created. And when you used to create matter, you're creating the isn't one and agent to and registering them with the factory. And then when you want Oh, all right, these agents with the new agents, This is possible in UV, um, as shown in the next life. So in the last line, we saw how type all right works. So in this life, we're going to see how the instance all right for a factory works. So here you have a monitor that you want to replace with a new type, but you don't want to replace all the components which are derived from a P. We muster monitor, but you only want toe replace a specific instance off the monitor. So you basically go down the test bench hierarchy and you say I want to replace the AP. We don't monitor because of the type A PB muster running toe with a new type that is the A P B new master monitor. So when this gets executed in the bill, face the distance component, get the architecture of the restaurant changes the a p b dot monitor changes to the MPB new muster monitor. Okay, uh, coming to question nine this is again a protocol question on the number protocol. What is the difference between the HB and Excite Protocol? I think in one of the previous lectures, we saw the difference between a hitch being an A P B protocol. HB is basically an advanced high performance, but but these are used for connecting components that need higher banquet on a shared bus. But if you look at X, I it is useful for higher bandwidth and low latency interconnect. This overcomes the limitation off a shared was protocol. He excites basically an enhancement from his be. It supports multiple outstanding litter transfers, fascinator types and separate read and write parts. We will see in detail in the next late. So what you see in the slide is basically the amber evolution. So ask the chips got complex, there is a requirement for higher bandwidth, and hence came the requirement for new protocols. So if you see 1995 that was only an A P B protocol, but with raising complexity and higher bandwidth requirement, they had to come up with a hitch, people to call and then the eggs. I was an improvement in terms off bandwidth requirement for an HB, and then this was increased with the Excite for and the CH I. The kind of architecture do you use depends on the kind off products that you're making. So he had me CIA associate with an ACSI interconnect. So here you can have multiple masters connected onto the interconnect and you can have multiple sleeves. You have an accede to every bridge like Harvey Saudi, HBO, PPV Bridge. The course here can talkto different slaves, and it can basically have multiple outstanding requests from the CPU core to the memory and CPU core onto the external bus interface. So this kind of an architectural supports higher bandwidth and low latency requirements that is needed for a system today come into question, then explain transaction level. More bling in New Veum transaction level models represent components at a set of communication process, So you're basically abstracting the different components. I'm then using this higher level of obstruction to send her transaction between a producer and the consumer. So if you pick a design, you're probably wiggling reports at their docked level. But when you want to send something from and component at a ubi, um, architectural level, you will probably send a total transaction level. This is very leveraged when you think off a sequence or in the driver. The sequence Aaron Driver are connected at their transaction level and a sequence of saying the transaction to a driver. The driver consumes this transaction, and then, since this data onto your design, the same with the monitor in the scoreboard interaction. The monitor basically captains. To do that, that is coming from your design and sends the state off for some kind of checks. In a school board for transaction level, modeling is basically usedto achieve this kind off higher obstruction. Thank you 4. Interview questions on GLS/SV/UVM: I come back to the system, Will look, you ve interview question series. Doesn't the pact three of the series that's get started Christian live in What is the difference between you art and SP? A protocol As you know, as you might know you, what stands for universal a synchronous receive and transmit as you see in the name. It's a synchronous in nature that is, there is no clock between, but there's no clock shared between the master and the sleeve. In simple terms, you are two lives on portrait agreement. So you basically tell you basically need to have an agreement between the master and the slave on what moderate the communication is going to pick person SP, on the other hand, has a master clock with such the block rate for this live, we will discuss in detail in the next late on the base under differences. So in the slider have taken three serial communication protocols and try to explain them under difference between them. The EITC, as you see, is a two line protocol. It is very cheap to maintain I and it has a clock and data line. The master drives the data on a particular club, and the sleeve kind of agrees on this clock. And because the data s p a on another, hang his ah serial protocol, where you have the s clock, which is being driven older slaves. A slave is selected based on the chip select. So if you want to say, like the wise one, the master will pull the chip. Select low for device one. The U work on another hand has a not X and V X been connected here. There is no clocking between the master and the slave, and this is only based on the agreement off border it between the master and the slave. The D transmission takes place, so there's a start off frame because usually a falling edge. So when a falling edge occurs on anti explain, there is a border it calculation and based on the border, it the free Miss Samford. Question 12. How can sequence get exclusive access to sequence, Sir, what is the difference between grabbing block? So, basically, when you have multiple sequences that are run on a sequencer the sequence of our bridge to grant access toe eat sequence on the sequence item boundary Sometimes the sequence might want exclusive access to a sequencer, which can be performed using and grabbing block the basic difference between a grabbing lockers. The grab on the sequence of this quarter takes immediate effect, and the sequence will get up. The next sequence are about arbitration. Hold a lock sequence. We'll wait until the sequin get it. Next available slots. The grabs can be used for some of the sequences, like the interrupt sequence. So basically, when there is an interrupt race, you'll have the service to interrupt service routine. So you will probably immediately grant access to the sequencer rather than waiting for every sequence to complete. So here is an implementation off a sequence where a lock issues. So here you are, locking the child sequencer thing. I need exclusive access for this particular sequence, sir. So if Sequined one wants to send a transaction, it has to wait till all the Lakis unlocked. So if there are multiple sequences locking the sequencer, they will get, they'll be arbitrator and they would get access as per the request. But if you grab if you send a grab request from this sequence, the request currently goes at the top of the stack and it is granted ones ongoing sequence is complete. Okay, The next two questions are related to the gate level simulation questions and usually in an interview. There are from a past experience they have always been Get level simulation questions if you are attending digital verification. Quick interview. So the question 13 is what is get level simulation and lays it necessity. Yeah, get 11. Simulation is used to boot the mostly confidence off the implementation. Basically, it is used as a sign off for your design. Get level is very, very much important because the critical time in parts off a synchronous design asked by S . T. So this have to be 14 jealous. The constraints that is used in SDA also needs to be verified, So these are cross verified against the GLS. If there is any black boxes in your equal in check, this cannot be caught in any other way, so idealised becomes necessary. If there are unintended initial conditions, you need jealous for switching activity and power estimation. Also, sometimes jealous used. I'll explain in detail in the next laid on the floor that is used. So this is a typical design flow. Let's try to understand. We're gate level simulation comes into picture, so you have a higher level. Are Pierre design you? Can you basically do a functional simulation to verify that your register level obstruction is clean? Then this sister abstraction goes through the synthesis flow. So during synthesis, you have constraints Notre property to your design. So once the synthesis is true, you get a get level net list. The gate level net list is also called a synthesis necklaced. So here you are on zero delay or unit Villa simulation, the chick, Whether you have whether the intention might just with the actual design, then in the floor, you basically take it through the pleasant road and you got you get something golden extracted net list. So here in the extractor net list, you also get something called a STD file, which is basically a no dating the delays off your nets. This is more off a real time simulation, and this is used to check all the conditions that explained in the previous slide. So for a dealer flow, you need a gate. Levin let list a library, sell information, and the delay information. These are all promoted from the backend team, so you're under jealous. If jealous buses, there is a sign up for your product. If jealous feels there might be genuine timing issues which needs to be reported to your back in team. Yeah, and they will generate a new necklace down in the staff and you go through the floor till all the timing is clean. But there are a few challenges that are associated with running a Geula simulation. So let us see. What are these challenges? Firstly, jealous is ready. Slow for Nicolas Simulation, the timing chip. You need to remove all the single anizers, basically the first flop offer. Synchronizer will always be matter stable, so you need to disable timing for this Using a T check file. You also need to come up with an optimal list off tests to ensure that year jealous covering most off your design, the engineer stand to get easily lost during X propagation D book. Also, as I mentioned, there is a constant change with Net list, and each net list release may need a lot of rework in terms off the force. Hey, I don't change us so delis in itself is a very painstaking process in the gratification, but it's a necessary evil. So this brings us to the end off the first part off me system in a long interview, questions Thank you for your time.