Static timing analysis interview questions | Kiran Bhaskar | Skillshare

Static timing analysis interview questions

Kiran Bhaskar, Teacher

Static timing analysis interview questions

Kiran Bhaskar, Teacher

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4 Lessons (24m)
    • 1. Introduction

    • 2. STA flow interview questions

    • 3. STA Timing arcs , Unateness , Data path , Clock path

    • 4. Reset and clock gating interview questions

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About This Class

Static timing analysis interview questions series is an initiative to help students/professionals who have basic knowledge of STA to quickly ramp up for an interview .The course intended audience is beginners who are looking to get into the VLSI industry .

The course is structured as 4 part series addressing the following interview question/concepts .

  • STA flow interview questions
  • Timing arcs , Unateness , Data path ,Clock path , Asynch path interview questions
  • STA Setup and Hold interview
  • Reset and clock gating interview questions


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Kiran Bhaskar



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1. Introduction: Hello everyone. Welcome to the static timing analysis interview questions series. My name is Karen buskers, and i'm looking into VLSI industry as a principal engineer for more than ten years. Now. This is the part one of the CDs. And today I will be covering some of the basic interview questions that are asked in a static timing analysis interview. Let us begin. Before we start the course, let us look at some of the course requirements. You need to have a basic sta background. Some digital design concepts will be helpful. And sometimes on Alice's knowledge will help you in understanding the course. Let us look at the cost structure. Because structure is split into four parts. The first part is covering the STA flow interview questions. The second part is covering the timing, OK, interview questions. The third part is the important setup and hold interview questions. And the last part is discussing about resetting, clogged, getting interview questions. Coming to the course objectives, the courses to help students currently having basic skills in static timing analysis and physical design to quickly ramp or fora interview. If you've been following my LinkedIn profile, have been regularly publishing daily interview questions on sta to help cover a broad range of concepts. So let us not waste any time and begin the learning journey. Thank you. 2. STA flow interview questions: Hello everyone. Welcome to the S-T-A-R interview question series. The first Partisi introduction to sta and flow. Let us begin. To begin this course. Let us understand how the STA flow works and wherein the asic design flow SDA is used. So basically you have the arterial designer who writes the RTL and it has verified with a testaments where design verification engineer. Then it goes through a logic synthesis and DFT insertion. After these two stages, a preload sta is performed. This may not be with the accurate delay information. This has an input of your design constraints and approximate delay model, which will help to do a first sta on your design. So once the design is synthesized, it goes to the backend engineer for flood planning and clock this indices. So after floor planning and clock biosynthesis, we do another round of an STA analysis. So this is basically a D estimated parasitics. You'll still have the constraints from your design. And you will do when sta, This is not considered as a sign of because this is with the estimated parasitics. After you do a placement route, you have the real delay information. When the SDF format and this delay information is fed to the SDA engine. And with the extracted parasitic information and with the constraints, the tool will do a timing analysis on your design and it will generate a report. So now let us try to see what are the inputs and outputs of a SDA tool. So the STAT2 needs D delay information which is either in the SDF is a standard delay format or the SBAR format. It then needs the gate-level netlist. This will be the net list that is synthesized from your RTL. Then you, then it needs D SDC, which is d, B leg constraints. It's the design constraints for your design. And then it needs the Library Information. Belabored information contains D settled beliefs. And then it generates the timing report and D timing window. Now that we know where an asic design flow USDA is performed and the inputs and outputs for an STA engine will try to understand what other types of checks that are performed in the SGA. We have the setup and whole check. We have the research removal check. You have the clock getting checks. We have minimum period and pulse-width of clock ticks. And we have some design rules checks which are performed in the STA. We will discuss this in detail in the coming lectures. Note that we saw that the texts that are performed in an STA will try to see one of the files that is used as an input for your SDA engine, which is df file. So what does an SDL file and what does it contain? The SDF file contains D delay information. The delays like module, part delay, device, interconnect delay or delay are all contained in your SDL file. Then you have the timing checks like setup and hold, recovery, removal, skew, width, period are all part of your SDL file. Then you have timing constraints. Then you have timing environments, which is the intended operating timing environment. And then you have incremental learn absolute delays. Will try to see what is contained in an STL file in example in the next slide. So here is a SDF examples for cell. The cell here there's a D flip flop. So this contains D. As I mentioned in the last 30, it has the delay information. So here you have two pots, which is the clock to Q and clock to Q. And this is containing the minivan Maxwell is for these spots. And then, and then we have the timings XX section, the timing check section. And to specify the limits in the way in which the signal can change. Or two signals can change in relation to each other. So for a reliable circuit operation, this timing checks has to hold. The EDA tools use this information in different ways. The simulation tools issuing warnings when signal transition, while ladies timing checks. The timing analysis tools identify the delay paths that may cause timing check violation, and may determine the constraints for these bots. Thank you. 3. STA Timing arcs , Unateness , Data path , Clock path: Welcome back to the STA into question series. So this is the chapter two of the series. And we will be discussing about D timing arcsin circuits. Let us begin. So what are the different timing circuit? You have D cell arcs and you have D networks. The cell blocks are basically the arcs inside D cells in your design. And the net arcs are usually the arcs that are connecting the two cells in your design. Let us discuss this in detail in our next slides. The next question is, what is uniqueness and timing arc? We have three types of units. You have d positive unit, you had the negative unit, and you have a non unit. A positive unit timing arc is if a rising edge in an input causes a rising edge in an output or no change in and output. It is called a positive unit. Ora. Falling your gin and input causes, causes a falling edge on the output or no change on the output. It is called a positive unit. And negative unit is, as you imagine, is just the opposite. A rising edge on an input causes a falling edge on and output are, and no change in output. Or a falling edge on the input causes a rising edge on the output or no change on the output. It is called negative unit. The third type is di non unit. The non unit is basically a change of output cannot be determined by changing input. So let us see the examples for all the different types. A good example for a positive and a negative unit is a buffer and a inverter. So what happens in a buffer? A rising edge in an input, Kazaa, rising air Jeanette output. So it's a positive unit. A falling edge causes a falling edge AND outputs, so it's a positive unit. Similarly for an inverter, a rising edge causes a falling or GND output. And a falling edge Janine port causes a rising or GND output, so it's a negative unit. Let us see other examples in the coming slides. Connect. The next question is, is an aggregator positive unit or a negative in here? Let us try to understand. So for instance, here you have a rising edge on input a. Assume b is one. Then you have a rising edge on output. And assume b is 0, the output is no change, so it's a positive Inuit. Similarly for the arc here, you have a raising your John B. If a is kept constant or if h sub 0, then you have no change. If a is kept to one, then the output is a rising edge. So it's a positive unit is the same case for the falling edge. So you have a falling edge. If the output is no change, there is a beta is 0, then the output is constant. If b is one, then you have a falling edge. Is the same for this are. So AND-gate is a positive unit. So in the last lecture we saw an example of an AND gate which is a positive unit. Let us now see a NOR gate. So what happens in a NOR gate? When you have a rising edge in a? You have a falling virgin. B. If B is 0. Else if b is one, the output remains unchanged. So it's a negative unit. Is the same logic for this arc. You have a rising edge. And if you have a falling edge, if there is a no change. So this is negative unit is the same for falling edge. For the falling edge, you have a raising edge if B 0 and you have no change if b is one. So you're NOR gate is a negative unit. So or as a positive unit and NAND and NOR is a negative unit. Let us see in the next slide what happens when we take the XOR example. So let us see the example for an XOR gate. So when, when there's a rising edge on a, when B is 0, you have a falling edge. And when B is one, you have a reason to urge. The same case for the B input when you have one and when you have a falling edge, and when E is one, you have a rising edge. So what does this conclude? There is no clear relation between D, input and output here. So XOR is a non unit, is the same case for the falling edge. Or the falling edge. You have a racing, you're given B 0 and falling Edwin BS1. So XOR gate is considered as a non unit. Let us see where this uniqueness is used in sta. So in the previous slide we discussed do different unit concepts. We will try to see where this is used. The unit concept is used in the file or the timing file. So if you open it up live file for a buffer, you will see the timing sense, that is for a2 y, let us output and the related pin is a. It is, it is shown that it's a positive unit. Similarly, this is an AND gate example. Here you have a two y, that is a pin, which is a positive unit. And b2 by, as we saw for an AND gate is also a positive unit. So in the previous slides, we understood the concept of uniqueness. Now we will try to understand the different paths that are used for timing analysis. We have the datapath, the clock path, dichloro getting pattern d i synchronous path. I will show each of these in detail in the coming slides. So the next question is, what are the different data paths? But different data paths are, basically you have input port to a register, that is this part here. You have register to register, that is clock to Q. You have registered to output path that is from here to here. And you have a path from the input port to the output port. These are the different data pots. So what are the different clock paths? The different clock patch here is I clocked path from here to d. From the input port we are clock pin. Basically there might be many buffers between these signals going from the input port to your clock pin. So here in this slide there are two clock paths. The next question is on the clogging path. So many times in your design, you may need to get clocks to reduce the dynamic power consumption. So here in the circuit, you have this LD, which is a gating signal for this clock, is not part of any clock, but it is used for getting this clock. So it is used as a plug getting path. The path is d are synchronous path. Here we see an asynchronous spot from your research into your receipt of your flip flop. So in today's lecture, we discussed about the timing arcs n D differing data paths. In the next lecture we will see how violation occurs. What are the equations to solve your problems? Thank you. 4. Reset and clock gating interview questions : Welcome to the Chapter four of the S-T-A-R interview questions. So today I'll be discussing a body researching club getting. Let us begin coming to the question first question, what are the different types of research? You have to synchronously certain you have D I synchronously, sir. If the reset affects the state of the design only on the active edge of the clock, we dominate us synchronously, sir. You, the reset affects the state of this design asynchronously. That is whether there is a clock or running or not running, then the design, you seem to have a synchronous research. One important point to notice, we cannot afford to have glitches in the research signal as long as it is meeting the setup and where timing. So if a reset signal is generated by a set of internal logic signals in your design, synchronous reset is d, only go to options. As there will be glitches formed by mingling, mingling of d, different conditions. For the designs with a synchronous research datapath is independent of d research signal. So logic levels in data but less. This means that we can achieve higher frequency using asynchronous resets. The design can be researched even when clock is gated. Also, there is no workarounds needed during synthesis, as in case of D synchronous desert. The only condition for an asynchronous reset is it needs to be glitch free. You and a small glitch on the Reset can. These are DI, design. So we saw in the previous slide, what is the difference between a synchronous are known as synchronous research. So what are the things to note during a research? The assertion sort of for a flip flop with our synchronously cert assertion of research, research D flip flop asynchronously. The D assertion of research gives D output of the flip-flop unchanged. The state of the flip-flop will change only on the arrival of the next clock pulse. There are two senior scenarios here. The clock is glaciated during the D assertion of research. The clock is running during the, the assertion of the research. In the case of block B, assertion during clock is greater during video session of research. In this case, we can safely be ESRD research AND gate the clock after the d assertion if the clock is running during video session. In this case, we need to take care of the recovery and removal timing of t, the assertion of research. There D assertion of research must be synchronous with respect to the clock. And researching colonizers are needed in this case. So Howard most designs modeled. So most designs our model to have a asynchronous research associate and synchronous reset d assertion, in which case you need a research synchronizer. We will discuss this in detail in the next slide. So what does the research synchronizer? Research synchronizer is basically used to model the behavior that I described in the previous slide. That is asynchronous reset assumption under synchronise. These are d assertion. So here you have a clock and then a synchronous research. So when you have an asynchronous reset here, the research inclines or output is basically, it Communist actually causes the output to go to 0 because this register is VSAT. And this will, these are d functional registers here. So an assertion will synchronously D registers. Let us now consider the research BY assertion case. And the restart is D asserted. That is here. You have d, d assertion here. It will wait for the clock edge here. Basically on the first clog, the reset is synchronized to the clock edge here. On the second clock, you hit synchronize to the clock here. This is to avoid any metastability. And then the result is ds2, all the functional blocks in your register. This is to avoid any research removal issues. So let us now see what is a recovery under removal check? I recovery under removal check is basically like a setup and hold for your research signals. So I recovery check and show us the d, d asserted. These are signal allows the clock signal to take the control of the output at the desired clock edge. For this, the reset signal must be stable, at least the recovery time before the active clock edge and remove all time after the clock edge. This can be modeled similar as a setup check with the difference of it being single-sided synchronous checks only. Coming to the last slide, we'll discuss briefly what is clock gating and its needs. Clock gating is basically a common technique used to reduce clock power by shutting off clock two modules. So here you have an enable signal and a clock signal. When the enable signal is high, there is a clock going into the flip-flops. And when the enable signal is low, the clock is cater to all your modules. So there are specific checks in STL that needs to be done for plugging. Will not discuss those in details in this course. But clogging is one of the techniques that is used to reduce the dynamic power. Thank you.