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Physical design interview questions

teacher avatar Kiran Bhaskar, Teacher

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Taught by industry leaders & working professionals
Topics include illustration, design, photography, and more

Watch this class and thousands more

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Taught by industry leaders & working professionals
Topics include illustration, design, photography, and more

Lessons in This Class

6 Lessons (40m)
    • 1. Introduction

    • 2. Physical design flow interview questions

    • 3. Floorplanning and placement interview questions

    • 4. Clock tree synthesis and routing interview questions

    • 5. Setup and hold

    • 6. Additional PD interview questions

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About This Class

Physical design interview questions series is an initiative to help students/professionals who have basic knowledge of PD  to quickly ramp up for an interview .The course intended audience is beginners who are looking to get into the VLSI industry .

The course is structured as 5 part series addressing the following interview question/concepts .

  • Physical design flow interview questions
  • Floor planning and Placement interview questions
  • Clock tree synthesis and Routing interview questions
  • Setup and hold interview questions
  • Additional PD topics interview questions

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Kiran Bhaskar



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1. Introduction: Hello everyone. Welcome to the physical design interview question series. My name is Karen basket, and I'm working in the VLSI industry as a principal engineer. This is the part of the series and today I will be covering some of the basic interview questions that are asked in the physical design interview. Let us begin. Before we start the course. Let us look at some of the course's requirements. You need to have a basic physical design background. Some asic flow knowledge, and some design basics would be helpful. Coming into the course structure. The course is structured in five different sections. The first section, I will be covering BD flowing interview questions. In the second section, I will be coding floor planning and placement into equations. In the third chapter, I'll be covering the clock resynthesis and routing into equations. In the fourth chapter, I'll be coding, setup and hold interview questions. And in the last chapter, I have an additional section on BAD interview questions. Coming through the course objectives. The course is to help students who currently have basic skills in physical design to quickly ramp up for an interview. If you have been following my LinkedIn profile, I have been regularly posting a daily interview questions to help cover a broad range of concepts. So let us not waste any time and begin the learning journey. 2. Physical design flow interview questions : Hello everyone. Welcome to the chapter one of the series. Today, I will be covering the physical design flow interview questions. Let us begin. So the first question is, what are the different stages in a PD flow? So it is very important to know how the flow works. So fast stages, you import your design, and then you floor plan. Then you take it to placement. And then you have the clock Chris integer stage. Then you route the design, then you sign off. I'll be discussing about each stage in detail in the next section. What is the import design stage? It is the very first day staging the physical design. In the synthesis process, the RTL code is converted into a netlist. In this import design stage, all the input files are read by d 2l. By using this information, redesign process will start. The second stage in a physical design flow is floor planning. What is floor planning? The flood planning is the process of determining the macro placement. So you have the different macros. You need to decide how you want to please these macros. And then there are power grids and IO placements. The IOS needs to be placed in the correct area. So floor planning is basically a process of placing the blocks macros in the chip slash code area, thereby determining the routing areas between them. It determines the size of the die. So when we start the design process, usually add an architecture stage. A die size is given. So it's very important we stick 2D die size. And it also creates wire tracks for placements of standard cells. It creates pause traps and specifies D pin connection. It also determines D IO pin pyridine placement information. Coming to the next stage become two. Placement. Placement is basically the process of automatically assigning correct position to the standard cells on the chip. There are two different types of placing. One is global placement. The standard cells are placed inside roughly. And then there is detailed placement in which the standard cells will place in sight rows, also called legalize placement. In placement stage, we check the congestion value by the GRC map. Coming to the next stage. It is the clock resynthesis. So in this stage, we bury the clock tree by using inverter Zen buffers. In the chip. Clock signal is essential to all the flip-flops. To give the clock signals from the source. We build the clock tree. In clock resynthesis, It is important is the process of balancing the clock skew and to minimize the insertion delay in order to meet the timing. And polar. Coming to the last two steps. The last two steps are routing and sign off. So before routing, the connection between macro standard cells, clock, IO port are logical connections. In this stage, we connect all the cells physically we de, metal strap. Routing is divided basically into two parts. One is the global routing, n. Second is D detailed routing. The global routing will tell for which signal, which metal layer is used. In detailed routing, the physical connections are done. After the routing stage, we come to the sign offstage. The physical layout of the chip is completed in the Sino stage. Insane offstage, all the tests are done to check D, quality and performance of the layer before tape out. So this gives them a brief overview of the different stages in your physical design flow. In the coming chapters, I'll be discussing in detail on the steps. Thank you. 3. Floorplanning and placement interview questions : So coming to the chapter two of this series, we will be discussing about some of the floor planning in floor planning interview questions. Let us begin coming to the question. What is flow planning? It is the very first stage of the physical design. The quality of the floor plan will design the total chip performance. The floodplain is a process of determining the macro placements, the IO port placements. And it is the process of placing blocks macro Cindy, chip core area, thereby determining the routing areas between them. It determines the size of the die and creates wired or wire tracks for placement of standard cells. So there are some of the important terminologies related to floor planning. What is a macro? So these are special memory elements used to store the data efficiently. And also they don't occupy much space on the chip compared to these memory cells. These are called macros. There are two types of microbes. One is a hard macro. So hard macro is basically if the circuit is fixed and we don't know which type of gates that are used inside. We only had the timing information and not D functional information. Then it's called a hard macro. Then there is a soft micro macro. The circuit is not fixed. We know which type of gates are going to be used inside. We know the timing information and also the functional information. And then we have the core. Core is D inner block which contains the all the standard cells AND micros. And then at the outer surface we have d. It is d block around the core, which contains all the IO ports. So the next question is, what are the different types of planning techniques? So there are three different types. One is d, r buttered technique and the second is the non return, and third is D mixed technique. So what does the difference in the abetted technique when the chip is divided into blocks? In our design, there is no gap between the blocks. The second is di non arbiter technique. In this design, there is, there is a gap between the blocks. The connection between the blocks are done through routing nets. And the third is mixed, which is basically a mix of both are better than no number. Third, design. Coming to the next question. What are the input files for your float mining? So you need your net, netlist. You need the standard delay constraints. You need the logical library information, the physically library information. You need the technology file. And then dy Un PDF files. Coming to the next question, what are the steps in floor planning? So there are main, two main steps. One is d, giving the aspect ratio, and then you have the core utilization. In giving the aspect ratio. Aspect ratio will decide the size and shape of the ship chip. It is the ratio between dy, the vertical routing resources 2D horizontal routing resources, or ratio of height versus the width. If the aspect ratio is one, that means the height and width of the chip is same. If the aspect ratio is 0.5, that means d. With this twice d times d height. Aspect ratio is basically height divided by width. The second is the core utilization. The core utilization will define the areas occupied by d standard cells macros. In other sense, if the core utilization is 0.7, that means 70% of the core urea is used for placing the standard cells macros in other cells. The remaining 30% is used for routing. What are the main steps in floor planning? The two main steps are placing the macros inside the core, carte de rose on microbes. So the main step in floor planning is placing the macros inside the core. After giving of aspect ratio and utilization factor of the chip. The size and shape was created. The standard cells and Microsoft placed on the outer side of the chip. In this slot plant stage, we have to Place de macros by some guidelines like fly line analysis, port communication, macro grouping, et cetera. Cut di rose on macros in the floor plan stage. But those are created inside of the core. To place the standard cells. When we place the macros inside the chip, the Roseville or Labda macros. So we need to cut Rosamunde macros. What are the steps? What are the steps in floor planning? Insert physical sales, inserting physical cells like absolutes, encapsulates filler cells, etcetera. These cells will protect the chips from faults. Then you have the IO placement I applied are placed at the boundaries in block-level. This IO pins are placed the D, input and output side of the block to interact with the other blocks and transfer signals. After that biological cell placement block is created in the die area to to prevent the logical cell placement. Diarrhea is only for the IO pins. Creating blockage. Placement blockage is applied in the floor plan stage to prevent standard cell placement. If we don't apply the placement blockage, there is a chance to overlap DDI standard cells on microbes be applied this RD macro area so that there is no chance to overlap the standard cells on macros. So the next question is, what is poverty planning? Planning is basically used to equally distributed power to these cells. We'd macros, standard cells or other cells. Normal connection will not distribute D power equally throughout the chip. So we choose special power design to carry power toward the chip equally. In this step, there are three levels of power distribution. You have the rings, you have this traps, and you have D rails. The rings are placed around the chip which got ED, VDD and VSS straps. It is difficult to transfer power equally from edge of the chip to the center of the chip. So we place horizontal and vertical nets in the chip from Rails to carry the power. Rails derails will connect D VDD and VSS 2D standard cells. So the next question is how to decrease D IR drop in a chip? So in polar planning, we mainly concentrate on the IR drop-in electro migration. In polar planning, PVD is mostly transferred through polished ramp. So we could decrease D IR drop. Ir drop is caused by the assistance. If resistance is more than iron rope is more, top metal layers will have reserved resistance. So I heard Robert decrease. So we choose top metal layers so we can decrease IR drop by adding more straps are increasingly, is trapped with. So another question that is commonly asked is, how do you fix D, electro migration? The electro migration can be fixed by downsizing the driver. You can increase the metal where you can add more VRS or separate cells. Coming to the next part of the physical design flow. It is D, placement. The placement is the process of placing the standard cells in, but also created a D floor planning stage. The goal is to minimize the total area and interconnect costs. The qualities highly determined by D placement. What are the inputs to D placement stage? So you need the gate level netlist. You had unit, the floor plan design, need the design labor Reese, design constraints AND technology file. So this brings us to the end of the chapter one-off. Bcd is in the Chapter two, we will be discussing more on d, pluc resynthesis and routing. Thank you. 4. Clock tree synthesis and routing interview questions : Hello everyone. Welcome to the Chapter three of the series. So today I'll be discussing on the clock resynthesis N routing. Let us begin. So what is clocked resynthesis? It is the process of inserting buffers and inverters along the clock pot to balance d, delay to all the clock inputs. Beefier plopped resynthesis, retreat. Clock as ideal. If we didn't blink, building plop, the skew and insertion delivering increase, which will affect the chip performance. To overcome this, we are constructing the clock tree by using the inverter Zen buffers. So the figure here shows the before block resynthesis and D after clock to resynthesis designs. So what are the main goals of the clock? This entasis, the main goals of the caucus interests is to balance the skew. To minimize the insertion delay, minimize power dissipation n. We de, logical DRC is. So what are the inputs required for your cluttering synthesis? As we saw from the previous chapter, that the clock resynthesis happens after your placement. So you need a detailed placement database. You need a target for your latency and skew. So this is important that a target is specified in this. In your nucleosynthesis. And buffers are, inverters are needed for building the clock tree. And then you need to complete the clock tree, DRC. What are the checks that needs to be done before the clock resynthesis? You need to have a completed placement. You need to have a pre rooted power and ground nets. You need to have an acceptable congestion in your design. You need an estimator timing and, and lasting easier HF and S. What is clock tree optimization? So there are many techniques to optimize your clock tree. One is delayed insertion. So this will improve the whole time. Then there is buffering. This will improve the setup time. Then there is buffer Relocation. So this will reduce this Q and D insertion delay. And then we have the level adjustment. You can adjust the level of your clock pins to higher or lower. And then there is good sizing. So you can increase or decrease D delay. To fix d max transition time, you add buffers and two, fixed d max capacitance. You decrease D. Length. So coming to the next question, what is crossed off? If this D, undesirable electrical interaction between two or more physical nets due to d cross capacitance between the two nets. So if you see here, you have two parallel running nets and that is m associated with associated cost capacitance. This has an impact on the input going into the net here. So what are some of the crosstalk reducing techniques? So you can increase the spacing between the aggressor in the victim nets. You can shield the net, maintain the stable supply. Increased the drive strength of the cell. Layer jumping. Victim that vert increase than the resistance decreases. Have a guard ring. And you can do sell sizing. Coming to the next step of your PD flow, it is routing. So what are the steps in routing? So you have global routing. It is done to provide instruction to detailed routing abort where to reroute every night. It provides logical connection to all this helps foster design is divided into small blocks which is called G cell. Each cell will have a horizontal line, vertical routing resources, which aim is to reduce the total interconnect land and minimize the critical part delay by using by using the global routing, we can analyze the condition. The second is d track assignment. It assigns each net to a specific track and lays down the actual metal tracks. The third step is detailed routing. So be very detailed routing. The connections are logical. In this theory, all the cells are physically connected. In this we specify the wire or interconnection in the channels specified by the global routing. Multi-layer information of the interconnects are also specified here. The violations that are created in the track assignment are fixed in this stage. It doesn't ruin the entire chip at a time. By dividing the chip into small block boxes. It will do the routing. The DRC is our fixed in detailed routing. And the last step is d, such and repair. It fixes the remaining DRC violations to multiple loops, loops using progressives layer as Spock sizes. So what are the goals of routing? So the goals of routing R2, meeting the timing DRC is minimizing the total wire length. Minimising the condition hotspot, and reduce the crosstalk. I minimize the number of VS. Thank you. 5. Setup and hold: Welcome back to the physical design interview question series. Today we will be discussing more district apparent whore interview questions. Let us begin. So I assume by now most of you don't know mortar set-up time or a world time is, but you're still not aware. I'll try to explain briefly. So setup time is a time before the clock edge by which the data to the flip-flop has to be stable. And hold time is basically a time window after the clock edge that the data has to be stable. Any violation between these two window will create a metastability. So let us uncover setup and whole concepts using this diagram here. So here you have a launching flop and capturing flop. So the data that is launched onto the launching flop goes through a combinational part and then reaches D capturing flop. So data has to reach before the setup time, before the clock edge, and it has to be held stable for whole time after the clock edge. So what happens if I set up a violation occurs? The circuit goes into metastability. So to our stability, we need to make sure that the setup and H4 times are always respected. So let us see an equation on how to calculate the setup n whole time. So you have d here, you have D T clock to Q delay. This is the delay that is for the data to be launched from this flip flop. And then you have d propagation delay. The propagation delay is basically the time it takes for the logic to propagate from this node to this node. And you have this setup time which needs to be basically honored for this particular flip-flop or this particular circuit. And you have the clock skew. Clock skew is basically the difference in the clock reaching this node to this node. So addition of all these should be less than the total time period. Let us see the equation now for the whole time. So you have d clock to Q here, and you have d propagation delay here. So this has to be held stable for t hold plus the skew. So this will give us an equation four. So this gives us the equation for the setup slack. Setup slack is basically a T period minus T clock plus t plus t setup minus p skew. So a positive setup slack means that d circuit is not metastable. And this is a similar equation for the whole Slack. Whole stack is basically T clock plus T minus T plus T skew. If the whole Slack is positive, that means there is still some margin available in D timing path. So let us see some of the interview questions based on this concept. So coming to an interview question and it may ask you, how do you take color setup coalition in your security? So this is based on your setup slack equation. The setups like is basically d PDF minus T clock to Q plus t prop plus T minus T skew. So a setups like has to be positive to avoid metastability in your circuit. So how can this be done? This can either be done by increasing the T0 period, which is indirectly reducing the clock frequency there. Do your time, your circuit. Or you have to either play around with these things. That is, decrease the clock to Q, or decrease the propagation delay of your combinational path. Reduce the setup time requirement of the capturing flop. Or increase the clock skew between D capturing lunch clocks. So these are the ways to tackle setup violation. We signed the last laid some of the approaches to tackle setup violation. Let us see in a real scenario how will the system. So one of the approaches is to increase the drives tenth of the datapath logic. A cell with better drives, Tempkin chats D load capacitance quickly, resulting in D lesser propagation delay. So your tree property uses and your setup slack turns positive. Use datapath cells with lesser threshold voltage. So usually in your cell library, there are the same cells with different threshold voltages. So you get, if you use else with the other shoulder shrug voltage, it will have a lesser delay. Another approach is to restructure the data path. So based on the placement of datapath cells, you can decide to either combined logic gates are split into multi stage cell so that the propagation delay can be reduced. And other way is to play with d p clock as a large distort, what you would probably do is show time your design into reduced frequency. So in the last two slides, we saw how to tackle setup violation. We will see how I will hold violation can be tackled. And hoard slack is basically d clock to Q plus t minus t minus t skew. So to have a positive hold slag, you can increase the clock to Q delay of the launching flop. Decrease the holding requirement. Decrease the clock skew between D capturing clock and D launching flop, or increase d propagation delay. So we will see some of the examples on how to do this in the real world scenario. So as we saw, we need to increase the propagation delay for fixing hold vibration. So what do you do? You basically insert delay elements. This is implicit that you can do to remove hold violations. Another way is reduced. Dr. strength of D datapath replaced this elevator. Similar sell-off, less strength. So this will increase the propagation delay of the cell. And the other approaches, as we saw in setup B, U cells with lower threshold voltages. For hold violations, we need to use cells with higher threshold voltages so that your propagation delay increases. Thank you. Another common interview question is, what is false but in your design? So false bots are basically pots that are not timed in your sta. This may not be time for different reasons. One of the reasons may be that that part is not possible architecturally. For example, if you take a mux, here you have a Select, which is selecting the mux and which is also in port for one set of intellect is 0. This part is not at all possible architecturally. So you can set a false button this design. So another interview question that is asked is usually under set up and hold time. So for that, you need to remember the setups like undo horse-like equation. So if you set up slack and horse-like is positive, that means there is no setup or hold violation. So from the figure arable, that TPR, it is ten nanoseconds. Clock to Q is two. T prop maxes for tea setup is one and the skew is one. So if we calculate here, the setup slack comes or 2x plus four nanosecond. So there is no setup violation. Similarly for the whole slack, you have block two, Q, t put up, E, hold, and peace. Q. So the horn slack is also positive. So this circuit is timing clean. So this brings us to the end of part one of D. Digital designer with a long interview questions. Thank you for your time. 6. Additional PD interview questions : Hello everyone. Welcome to this extra chapter on the physical design interview question series. So today I'll be taking you through some of the common interview questions. So let us begin. So the first question is, what are promulgating cells? So the power gating cells are used to overt static power dissipation. Dipolar getting cells are polis, which is leveraged 50 hertz, retention registers, isolation cells, n bar controllers. The second question is how to reduce latch up problem. So the early cmos process suffered a reliability concerns, became known as latch up. It resulted in circuits either malfunctioning or consuming extra superpower, or could be either inherent in their design, are triggered by voltage spikes on Io parts that could forward bias p-n junctions that you are connected to. So to reduce the lecture problem, you can increase the spacing between the bivalent and will increase the substrate doping concentration or use ground rings around the device. Another common question there, disasters waste nine get preferred over the market. If you look at it from a disease. From a device perspective, at the transistor level, no mobility of electrons is normally three times that of holes. So a NAND gate is faster and has less leakage compared to a NOR gate, so it is preferred. So the next question is what are isolation and retention cells? The isolation cells, especially since recorded interface between blocks which are turned on and always on, it is necessary to isolate floating power in ports. Similarly, retention cells are special flops with multiple power supply. When their design blockers, which those four sleep more data in all flip-flops contain desired stage to retain. Retain shin flops must be used. In the diagram here. If you see when there is a Power Don and an isolation happening. So you have an isolation cell here, which isolates this particular logic from this particular logic here. Okay, the next question is, what are the different types of cells that are used? So we have absolutes. These are used to avoid latch up problems. You have encapsulates. These are placed at the edges, go white sari damage at the end of the row. We have decapsulates the self-paced between power and ground rail TO white IR drop. We have filler cells, and these are used to connect gaps between the cells. We have ICD cells, these are useful club getting. We have bad cells to interface with the outside device IP. The power clock pins are connected to Pat cells. And then finally we have digit axles. These are used to check the IO connectivity. The next question is, what is the difference between a hierarchical designer, flat design had a current design has blocks and sub blocks in a hierarchy. And flat design has no sub-blocks, it has only leaf cells. Hierarchical design takes more time to run, and flag design takes lesser time to run. What are the types of blockages? We have hard blockage. It doesn't allow inverters, buffers and standard cells. We have soft blockage. It allows only inverters in buffers and block standard cells. And we have partial blockage. It allows both buffering 100 cells in a percentage value. The next question is, what does conditioner, how to fix them? When the available tracks are less than the required triumphs, this effect will occur, that is, the condition will occur when the signals are more than the tracks then conditionally locker. So there are different ways to fix them. Oneness, condition driven placement, we can adjust the cell density in congested area because the high cell density causes condition. Use proper blockage, modify D floor plan of D design. The next common question is, what is temperature inversion? And higher cmos technologies, surrealist increase when temperature increases, but when you are in the lower technologies that is below 65 nanometer, certainly lists have an inverse, inverse proportion to temperature. This is core temperature in ocean. The next question that is used is, how can you reduce dynamic power? So you can reduce dynamic polar by reducing the power supply voltage. Reduce voltage swinging all the nodes. Reduced D, switching probability, or reduce the load capacitance. Coming to the next question, what does contain reordering? Scansion reordering is a process of reconnecting the scan chains and their design to optimize for routing by reordering this kind chain connection, it improves timing n condition. The next question is in electric, but if you have a setup problem, where will you insert the buffer? We can insert the buffer near the launch flop. This will decrease the transition time instance decreasing d y already Lea. Therefore the overall delay and the arrival time will decrease, which will help de, setup violation. Next question is, what is metal slotting? Metals flirting technique for averting problem lake metallic Goffin, metal erosion. What are the power dissipation components? There are three power dissipation components. One is the dynamic power consumption, and that is the static port consumption. And the last one is dy, short-circuit power consumption. Dynamic power consumption and cosine signal goes through a cmos circuit change. There is a logic state change. By discharging of the capacitor. Static or leakage power consumption is polar consumed by sub-threshold currents or by reverse-biased diode Cindy cmos transistor. Short-circuit power consumption occurs during switching on bodhi in Mohsen PMOS transistor in these markets and the conduct simultaneously for a short amount of time. So this brings us to the end of this chapter. Thank you.