Learn Digital Electronics with Schematics and a Basys2 FPGA Board | Ajmir Goolam Hossen | Skillshare

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Learn Digital Electronics with Schematics and a Basys2 FPGA Board

teacher avatar Ajmir Goolam Hossen

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Taught by industry leaders & working professionals
Topics include illustration, design, photography, and more

Watch this class and thousands more

Get unlimited access to every class
Taught by industry leaders & working professionals
Topics include illustration, design, photography, and more

Lessons in This Class

26 Lessons (2h 20m)
    • 1. Presentation of the Course

      2:44
    • 2. Introduction

      9:21
    • 3. Download and Install ISE

      2:21
    • 4. Get a Webpack ISE License

      2:44
    • 5. Project Navigator

      5:35
    • 6. Logic Gates - Theory

      7:39
    • 7. Implement a XOR Gate - Practical

      5:29
    • 8. Implement Many Gates - Practical

      6:31
    • 9. Flip Flops/Registers - Theory

      3:55
    • 10. Implement an FDC - Practical

      5:13
    • 11. Implement an FDCE - Practical

      2:49
    • 12. Implement a Shift Register - Practical

      8:28
    • 13. Design a Debouncer Circuit

      4:44
    • 14. Implement an SR using FFs with a Debouncer - Practical

      3:50
    • 15. Multiplexers - Theory

      4:05
    • 16. Implement a Multiplexer - Practical

      4:16
    • 17. Counters - Theory

      3:17
    • 18. Implement a Counter - Practical

      5:18
    • 19. Adders - Theory

      3:04
    • 20. Implement an Adders - Practical

      5:11
    • 21. Random Access Memory - Theory

      4:43
    • 22. Implement a RAM - Practical

      6:54
    • 23. Finiste States Machines - Theory

      8:42
    • 24. An example of a Finite States Machines

      5:41
    • 25. States Transition Table

      5:49
    • 26. Equations for Transitions and Output Logic

      11:46
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About This Class

This course was designed to give students an opportunity to kick-start their skills to Design Digital Electronics WITHOUT the hurdle of having to code in HDL.

How this course works

Concepts are first explained, then demonstrated by using the ISE software from Xilinx. Coding in HDL languages will not be taught in this course but instead, Schematics will be used as it is easier for beginners. Students will only need drag, drop and connect schematic symbols together. Then Run through the flow of ISE to generate the bit file.The bit file will be downloaded on the board to see the results.

The goal is to quickly put together designs and try them on the board, without the hurdle of VHDL/Verilog coding. In this way, you will focus on how Digital Electronics works.

This course doesn't show software simulation but focuses on testing your designs straight on the board.

What will you need?

You will need to download and install Xilinx ISE software in the Webpack version, which is free. Ideally you will need the Basys 2 board, which uses the Spartan 3E FPGA, to verify your design on hardware.

 Content

The course is split in sections of the main building blocks of Digital Electronics such as Registers, Logic Gates, Random Access memory etc...

In each section there is explanation of various blocks e.g in the Registers section will be explained the Flip Flops and Shift Registers. After most blocks explanation there will be a practical activity on how to implement the circuit on an FPGA and verify the design on the Basys 2 board. 

Meet Your Teacher

Hi, My name is Ajmir and I've been an electronics/programming/science hobbyist since the age of 12 and obtained a Bachelor in Electronics and Communication Engineering from the University of Mauritius in the year 2001.

After graduation I attended a short course in Web Design, where I learned HTML, PHP and Java.

I've worked at various positions in the Electronics Industry, including Sales Engineer for electronic instruments, Lecturing in Power Electronics and Data Communication, Test Engineer and Debugging boards for UK Road Signs.

I've worked for nearly 7 yrs at Xilinx in Dublin, Ireland as a Product Applications Engineer, supporting Xilinx FPGA Design Automation Software tools. I became a specialist in Synthesis tools/Timing Analysis at Xilinx. I also worked with D... See full profile

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Transcripts

1. Presentation of the Course: Hey, guys, Thank you for your interest in the course. Learn digital electron ICS with schematics and f p g A board. This course is presented by Asmir. Ghulam Holson as Mere has a bachelor degree in electron ICS in communication engineering in a BSC in digital technology. He has worked in various engineering roles in a number of companies, including a lecture in information technology and electron ICS. He also worked at the multinational company Xilinx, whose co founder invented the F p g A. He worked for seven years there as a product application engineer for I S C and Vivid O. Toole's specializing in synthesis in timing analysis, where he worked with high profile customers on challenging projects in gained experience with real life implementation of technology and software quality. He is a passionate instructor and is curious about technology as ever. At the end of this course, you will be able to easily design basic digital systems for F p G ays using schematic symbols only by simply dropping symbols on a schematic and connecting them. You will be able to assemble and verify your design on a basis to board in no time this course was specially designed for the students to use visuals instead of coding to build digital circuitry, so you will neither use nor need the Novi HDL or Vera Log. But focus on schematic symbols. You will learn about the most useful digital blocks that will enable you to build almost any digital system E g. The shift registers multiplex er's calendars, ADDers and more, including finite states machines. After going through each lesson theory, you will be shown the practical steps to implement simple designs on F p G A. This consists of using symbols in the ceilings I s E software, connect them together at a few constraints and launch the I S C flow. To generate a bit file. The file will be ready to load on the board and see the design work right away. The course ends with the design from scratch of a basic alarm system. Using a finite states machine, you will learn how to derive the truth tables, find the Boolean equations and draw the circuit. The ideal students are those who are interested in learning digital electron ICS as a career or simply as a hobby. The approach used in this course is ideal for aspiring hardware engineers. You may be a computer scientist who wants to start working on embedded designs and would like to understand the hardware aspects. This is your starting point in understanding digital electron ICS so enrolled today and see you in the course. 2. Introduction: So what will you learn in the schools? You will understand the main elements in digital electron ICS. You will design and implement them on FB G. And you were the very fiber designs on the board using futures. And let's we will learn about the typical elements in digital electron ICS starting from logic gates than fifth flops. Shift registers multiplexes, counters others and subtract er's random access memories, Finance States machines. And in the FS um, section, we will design and other arm system using an F S um, from scratch. We'll make use off the icy software and we will make designs using schematics on Lee. So in this course, there will be no that son in VH. DLL very long, and we'll make use off the basis to board. Now let's take a look at digital electron ICS. They have two types off signals on a dog and digital. So, as you can see, digital is this size zero or one. Information is encoded in the sequence and pattern of the ones and zeros y four analog signal the value off the signal with very it will be a continuum, so a signal in analog can have all the values meetings arranged. So this is a difference between digital and analog, and these are separate. Feels in electron ICS, another electron ICS and digital electron ICS. This course is about designing in digital. Now an analog signal can be used in a digital system. By digitizing it, we normally use a chip cold A. D. C. And I look to digital converter, so it will approximate the signal into sequence off digital numbers which are by any remembers. They are examples of digital systems. We've a D. C Andi a sees. So here we have the outside world. We have a signal coming here on the signal will be converted into digital using an A D. C. And this will be process in the digital system and they are put with me in digital. Then we will convert the digital into analog so digital to analogue converter and we can use it in the outside world. Here's an example where we have a speaker in analog sending an analog signal to an A d. C. The EEC will process the analog on our put digital signals. This will be processed and the digital out will be converted into another hug and that can be sent into it. I'm speaker. In this case, we have an analog camera and the camera will send a signal to an a D. C. It is a digital system and back onto a TV. These are examples of digital systems without a D. C. In this case, from the outside world, we're sending digital input to a system an output digital signal, for example. We have a search. The switch is ours, the on off. So it's sending discrete signal to the digital system so it doesn't need an a. D. C. In this case, and our put here is going to be really the really works we've once and zeros, so we don't need a D. C in this case. And this one is a digital camera having digital are put. So you're sending digital output to the digital system, and the process signal is sent to a lead is that also works. We've 10 It's either on or off, so we don't need a decent. This case in this course will use speeches and push buttons as input to the digital system . And for our quit, we will use. That's and these will be found on the board in digital electron ICS. We have two types of elements, one with use clocks and one will not be cooked. The elements of the clock are used synchronicity, while the elements that are not clocked oh, use asynchronous e the pins for the synchronised elements will usually be fed by a global clock. For example, a ridged is a single US element. Why energy get will be an asynchronous element. These are the two main building blocks off digital system. We have the logic gates and registers or feet plops, and the gates will be asynchronous. Why the flip flops and registers will be synchronous. The hardware that we use in this course will be the basis to board. And on this board we have the F b G from Xilinx cold spot on free. This is a family name off this device, and we will use a USB cable to connect your PC to the board so the PC would provide the power for this board. This is a Zion X F P G on the board. This is a USB connector where we collect the USB cable to the PC. This is the on off switch. These are the push buttons they're switchers on. The leads are are put. The software that we will use is the Xiaoning Zycie version 14. That one on the design would be made in schematics. We'll use schematics on Lee. We won't use VH deal or very long. We'll use the icy floor to generate the bit file, and we will use the program impact to program the F B G. An impact is part of Design Ing's project designed with I see we would use schematic. There's with involved dropping symbols from the library, connecting the Cymbals together and adding ports. And we will use a fire call UCF, which is user constraints. Fire on these fires were add location constraints and the syntax that we will use is net. Look, the faction off the location constraints is to think the ports to the pad on the board. If you want to connect this boat to a particular are put on the board, we have to add this information in the UCF. Normally, we used timing constraints in design for refuge, but in this case we will leave it as default time income strength, which is done in a sick Um, if the two doesn't see any user time in constraint, it would add a period off 10 nanosecond by default. 3. Download and Install ISE: you don when I see how to go to resign. Ings that come and click on download. Here we are under down the beach, we click on I see design tools, and here are different versions off I see on the latest one available is 14 to 7, so we can download the version for Linux or Windows here, for example. Don't shit. I just click on Windows. So this is just a survey beach. So off the feeling the survey and sign up. If you don't have an account, all you signed in. If you already have an account, the down over his starting this. So once. The findings downloaded good to the application and find the father and then extract it because it's in the compressed form, for example, exists Onda, and this will give a folder It exists, so the folder will contain these files and began. Go ahead and click on X set up during the installation, you will have to choose. I see went back because it's a free version off icy available, and this is a final windows. Before installing server installation, the files will be deposited in a folder, for example, this is where my solution is. So if I click on 14 7 I see and I click on I see here So this will contain is for the been We contain all the the Bani Refiles not only did for example, if I go to anti 64 I can launch I see from this exit fired here 4. Get a Webpack ISE License: If you have followed all the instructions, you will be able to complete the installation off. I see what back. And also they will be this window that will be opened. And this is called the license configuration manager on. It gives some options here. So we have different tubs on the Aquarian license. There is this option. Get free. I see. Went back. So you have to choose is to get a free version off I. C. Webb back license before I click on next, I look at the manage licenses. So this is an example of how the manage my senses top. Looks like when you have a license. So I have my eyes. I sense set up. Yeah, As you can see, you're going to receive a dot and I see file from signings That will be your free work back license and you can do the license asked for those who, by clicking on Lodi sense, you can find a license. So that dot and I see you can place the dot and I see in a folder and find it. Here's how my license looks like is I think stuff and I see which I received from signings . So I place it in a folder and ah, I have to load it from this. So load, I said like it and I click on open. So at the bottom here, we can refresh. When we put a new life sense, we can refresh it. So when we look at all the features that are accessible for this nice sense here, so each one off this here is a future. So, for example, he had done ahead. So that's a feature from I C went back on. So as you can see here, it's permanent. So you can permanent to use this icy went back and I sense for ban ahead. Plan ahead is part of the I seen solution. We also have the i c with back my sense so that's permanent to acquire. Use this I since you said like this and he got next and click on correct now so that you will receive it that l I c filer through your email that you're going places in a specific directory. And again, though, did as I just showed you 5. Project Navigator: in this lesson, we look at how to use icy. This is a view off icy project navigator. When there's no project open now with open and eggs for an existing project, I will use open project. But now I will try open example I will open an example of project. I would choose this project. I'm selecting one project from the least a press. Ok, This message is because I've already opened this project before. Now the project is opened. This is the link to the project file. We have different. We do is here This is the part of the device clicking on this We give the design properties for this project. This is spot on six. This is a device the device name. That's the back age and we have speed. That's for timing purposes. The center The stool is xsd. The simulator is I seem the preferred language. These other fires in the project These three dots means that it's the top level. So you designed may form a hierarchy and this will be the top module off the hierarchy. And these are some modules to the top. This window is about the processes. The first process would be sin disease. Then we moved to implement design to rinsing disease. We right click and Rin. Since it is part of the flu in the consumer, the status will be shown. It would give some information about this will ensure that errors, Hear the warnings Now I'm running implementation prizes off Translate map and place in route. These are the messages and these other reports left Who has reach MMA and is going to do please and root If I had to open a fire in the hurricane, I just have to the book the comet and it will be open here. This is a drop down to see the sub module. If I want to add a new source, I will do project new source here. I can choose what type of source I want to add. Example Avery, Long module, aviation module or schematic to close a project will do five other clues to archive the project and we do project Al Qaeda all the finance we good to use it fine 6. Logic Gates - Theory: in this asan. We look at Virgin gates, we will see how they work and understand the relation between the output and their input for these building blocks. Here are the seven logic gates that we will look at the logic. Gates will have a number off input and one output for this gate that we call inverter. It has only one input wine for the other gates. You will see that they have to input. Let's take a look at the gates and and this ignore the two. The two here is part of the Xiling Symbol Library, and it just denotes to input and gates on nine gates. You see that the symbol, useful end and then look the same. Except that the small circle of the output or the NAND gate. This means that the output of the nine gates will be the exact opposite. Off the end gates. By opposite I mean, that the output will be one if the end get maybe zero for the same input. If the output of the nine gates is zero for the same input, the endgame would give it one. Similarly, we have all the piers off the gates such as or And nor they are the exact opposite of each other. And we also have the payer X or an ex nor there also opposite to each other. And finally we have the inverted gate. Next we will draw a table and this table is called a truth table. The truth table would give the output of the gate for all the possible input combination. Now, this is the truth table. Each row is a combination off input. For example, the first rule is 00 When input one is zero on input to is zero, you would have an output off zero on the second row. You will see that if the input 10 and the input to is one, you would have an output off zero. Sir Drew the input one is one. The April 2 is zero. So the output with me zero according to stable and lossy, we have input one an institute at one. This gives an output off one. You will know that the output is only one. When the input one as well as input to or at one Next we will take it out NAND gate and as you said. The name gate is the inversion off and engage so we will start with the truth table for the end gate and change it into an N gate. To do this, I will simply invert the output in each of the room instead of having 0001 We have 1110 and this is the truth table off the NAND gate. For example, If the input one is one and the amplitude is zero, the Arquit will be one. While we have an end, get the output. We have been zero. Next we look at the or gate. We'll start with the truth table for the NAND gate and we were edited to get the truth table for the or gate. As an m suggest the organ. We have an upward of one. If either of the two input at one, so at least one off the input should be at one for the output to be one. This means that a row two and road free would be one, because on Row two, input to is one And on row three, the input one is one. So the output will be one rueful will also be one because it has two input set to one, and we just need one off these to set the output to one. So now we have two. It would be one. No one would be 00 so that I put with zero, because neither off the input offset to one. So the upward we have the pattern 0111 Next we look at the North Gate and as we said before , the nor gate will be the inversion off an or gate. So we simply have to reverse the bits in the upward in our truth table to get that off the north gate. This is a truth table off the nor gate, and the output has a pattern. 1000 The next surgery gate that we will look at is the X or the X Here means exclusive, so it's an exclusive or gate. It is similar to an or gate, except for a case when both inputs are set to one. As we said for an or gate at this one off, the input should be set to one for the opportunity. One. Why in the X or gate? If both input are set to one, the output will be set to zero. I will modify the truth table for the or gate to get the X or gate. The first free lanes would be the same. Why the fourth line would have to be inverted. So for the case of 11 the output with me zero and the rest would be the same US an or gate . This is the X nor gate. And as you have guessed, the X nor gate is an exclusive nor gate and the ex nor gate will be the inversion of an X or gate. So I simply have to reverse the bits on the Arquit on our truth table. To get that off the X nor gate, you will notice here that the output is one is both the input offset to the same value. For example, if input one and input to our set to zero, the output will be one. Why the evil set to one and one. The output will be one again. And also when the input one and in. But you are set to one. The output with me still toe one And let's see, we have the inverter gate, also called the Not Gate and the Truth Table. We have two entries because a number of input here is one. When input is zero are put is one. And when the input his one, the output is zero, So it's an inversion. 7. Implement a XOR Gate - Practical: in this lesson with implement an exo gate on the board this ex or get will have to input on one foot for the input. We will make use off speeches. Why, for the output will use a that on the board that's open. I see and create a new project. I gave you the name and I said, the top level source type two schematic because next he is a project. Settings should be us on the screen. Finished creating the project. Now I can add a new source, My doing Project New source and I was at a sciatic. I give it a name top, then finish. Now it's creating the schematic. It's a blank schematic now, cooking on the Cymbal tap, I would choose a logic in categories under symbols, I would choose X or two are we select the X or from the symbols and bring my cursor on the skeleton. I do not need to drag and drop just Celic and bring the cursor on the schematic. This is the X Colgate. You can zoom in and zoom out. I can move it. I need to add both the input and output, so I click on it and then click under input and output to create the ports. These boats are accessing internal wires from the outside By default, it will have a name starting with X l x n We can change the name by right. Clicking on it once the name has been changed can save it Now we add a new source and this will be implementation constraints file and I will name it. Top this file. We have an extension dot UCF This is where the constraints for this project will be stoned in it. I will add the location off the different parts so that I can think it to specifications. Let's and searchers on the board. The syntax to add a pad is net, and I need to give the name of the port, then lock equal to the pat name on the chip. So we have three ports. 1st 1 would be input one which is a input input to and output one input one with other location P 11 input to We have the location l three and I'll put one. Will be I'm fine. So here p 11 and L three, we go to switches while the M five. We go to a lead for the output. Once I'm done, I can save it and I can go in the design top right pick on generate programming Feiler and then click on Run All or Run. And at the end, a bit file will be generated. This made fire there will have to be loaded on the chip, and this is done for the tool impact. Now I can connect the USB cable from the boat to the PC. I would choose the Dub it my posts bridging on impact. It would show that the programming has been done successfully. Yeah, you would make use off the two features on the right. When the switch is pushed up, it's a one whence pushed down. It's zero, and the lead will be shown on M five you received at the pattern before the truth table are shown before 8. Implement Many Gates - Practical: in the last lesson. We've implemented an X or gate on the board this time with add more gates to create a more complex design, I was told by creating a new project and give you the name on Gregan finish. So now I can add a new source project new source schematic. Now we call it again top Next. I would go to categories on symbol. So that logic and I was like a couple of gates. He I'm selecting end and to in nor gate an ex nor gate. Here I will use the three gates on the left to drive the three gates on the right. Now I'm connecting the wires. The the operate off. These two engages with Dr the input off the north gate. The are put off the x or gate with Dr One input off the or gate and one input from the X No gate on the, uh, put off that end gate. We also drive the input of the X No gate. I was under ports. I can now rename them. I would choose some appropriate names for them here. I'm using in one into in free to name the input off this design. And likewise, I'm renaming the output both names next with at an implementation constraints file, as we did in the Lost Essam here we had luck constraints to nets, So same thing I will copy and paste. I will add locks to the input that we go to parts that are link to speeches. P 11 to every will be input features generate the programming, the trial. And when this finishes, I can open impact to program it as we did before. Once the design has been loaded, I can use the stretchers and check the let's at our own to confirm if the design has been correctly loaded on the board. 9. Flip Flops/Registers - Theory: in this lesson, we will learn about an important building block off digital electron ICS, and these are called flip flops or registers. This is a symbol that we use to represent defeat. Plop A D means data. This is a common flip flop that's used in digital electron ICS. So we have data in and data out determining our input data, and I put data here and we have a clock. This clock will feed the flip flop, and as a triangle symbol here represents edges, so the flip flop would be triggered on the on edges. And in this case, it's triggered on positive edges. So a flip flop is a synchronous element that's triggered a bleated on Lee on edges on clock edges. This is a table that shows the different transition in the fifth plop. So when the clock is a positive edge and the data is zero, the ah, quit with me. Zero. The airport that will be clock out with zero one day is a positive edge. On the data is one the are put that would be clock out is the one. So whatever data is under input will be clock out on postive edges, while for the negative edges, there won't be any change. So the detail will stay the same on negative edges and the rest of the way forms changes with on the Oakar on edges on positive edges. In this case, this is the post. Steve edges the deaf eclipse. Now, this is the negative edge. Data fit Klopp. And as you can see, the only difference from the positive edge free plop in the symbol is that these little circle at the clock input. This means that the flip flop would be triggered on negative edges. So, as you can see in the truth table one, the clock is at a negative edge and the data is zero. The detailer will be clock out is zero on in negative edge. If there is a one, the detail that will be clock out, he's one. And on positive edges, there would be no change to the detail will stay the same. So the foot Klopp is on the tree. Good on the negative edges. Now, if you connect a serious off detail, flip flops are shown in the diagram. This we call shift register. This is because the data on the left will be clocking to accuse your and the detail that was on the Q zero would be cooked in two Q. One. The detail that was on the key one. We clock out too cute you. So what would happen here is that the detail that's under left would be clock out two Q zero and the data that WAAS on the Q zero would be clock out. Two. Key one. The detail that was on the key one would be clocked out on the Q t. So the same day, that would be shift at each clock. If I put it one on the D, it would be clock out to Q zero, and in the next cycle it would be on P one and the next cycle. Be cute. You. So it's like a chain off it plops. 10. Implement an FDC - Practical: in this lesson, we will implement a basic people on the board by making a small design with icy. First, I'm creating a new project. I'm calling the project F D C, and these are the settings for this project. Now the bank project is created. I can add a new source and here I would choose schematic. I would use the name up on finish. Now the bank schematic is created. Choosing the symbol stamp. I was said that fit flop in categories and here I would choose the basic tips off FDC. Click on it, click on the schematic to drop it. I will add the boats and I will rename the ports to the correct names. Now I'm done. We've renaming the ports. I can save it. And here we add a new source, which is an implementation constraints pile. Give you the name on finish Now the top dot UCF is created. I can add the constraints mainly the location constraints. So I will use net and look so I have net in one. Are we lock it to this location. I'm copying each off them and I'm editing to the correct name. So have in one oclock clear and I have out one and clock is like to be eight, as usual are we lock in 12 p 11 which is a switch Julia do a seven, which is also a switch. And at 12 AM five, which is a lead on the board, the small design is done. Now. I can right click on generate programming file and click on Rerun Old or Run. I can now use the impact software to program the top that bit file on the board. 11. Implement an FDCE - Practical: in this lesson, we will modify the previous design. We'll change the FDC, which is a basic fifth up that we've used. We will change it into an F. D. C. This flip flop is slightly different from the previous one in the sense that it has an enable pin on the flip flop so you can use it to disable the flip flop or enable it. When it's disable. The flip up won't change. It will not respond to any cock edges. It's only when the enable pin is set to one that the fifth up with work. Normally he's a previous design opened. I'm deleting the fifth up and I will go to symbol. I'm going to choose FDC. Replace the FDC in the exact position off the FDC that I've removed and you will notice that these an additional pin called CE I will add a port to it. I will rename it to block unable. This clock enable will be an original port in the design, so I would have to add a line for the location in the constraint fire four This clock enable This is a line that I would add in the UCF a result Lee Clock enable on the location at three. Now that the design is done, I can save it and I can run, generate programming bit file. Once it's done, I can use impact software to program the bit file on the board. Here is a demo off the design loaded on the board. Who is this which would provide the clock enable? You will see that if the clock enable switch. L three is set to zero. Nothing happens. If I change the input, the Arquit will not change at all. If I said the enable to one, then the input will be registered and you will see the input change. This is how the any book pin can be used to disable the flip flop. Oh, enable it. 12. Implement a Shift Register - Practical: Indus Essam with design is shift register using a few flip flops connected in a chain, and we really implemented on the board to see how it works. I would create a new project and we call it Schiff, Reg one and the setting asked for those. I can now add a new source, which is a schematic with the name top. Once the schematic is created, we select the flip flop categories and I would choose FDC. I will choose more off them and add on the schematic, and I will connect the queue to the D of the next. We connect the clear pins together. So here have five FTC's and the Clears are connected together. This will make a clear line, and we clear all the flip flops at one group. The clocks will also be connected together. So all these Phipps ups will be clock each time by the same clock. And similarly, I will connect the C E pins together. And now I will add the boats. This is a port for the clock. This is a port for the D for the D input. This is unsure. Data will be coming to the shift register, and I would add a port to the clock enable and a port for the clear pins. I would also add Ports on the Q are put off each Phipps up, - and now I'm giving the correct name to the polls, - and this is a final are put in the shift register. I will name the output Q zero Q one Here, too. You're free and Q four. - I can save the project already, and now I will add the implementation constraints. File the UCF to add the location constraints. I would have input in zero clock. Look out to be eight earlier on CNN and the Opera Q zero to queue. For once that's done, I can save it and run the generate programming. Feiler. And once this is created, I can use impact to program the beat file on the board here easily to demo off how the design is working The first, which on the right will be the input. It will not change the ship fridge tha as long as the second switch on the right L three is set to zero when is set to one. If P 11 is set to one or the ark would lend lights up. If the seconds which from the right is set to one which is enable and P one is set to one, all the output leads will be turned on. This is because the clock is very fast. You won't see the actual shifting off the ones through the shift register. This is why you will see all the leads would be light on our soon as P one is set to one. When it set back to zero, all the fifth flops will be in the state of zero and the lead would be turned off, so data has been shifted into the registers. 13. Design a Debouncer Circuit: who will make use off the previous project. I will add a new source which is a schematic, and I will call it the Bouncer. So it will be deep. Answer the SCH and now the demands. A schematic is created. This is just blank. At the moment I was started by selecting FDC from the fifth top categories in symbol. I will use three of them. I would think them as in a shift register. So the output Cuba and go to the next fifth up through that been, de, I will add the ports for the I'm now linking the clear pins. I'm also thinking the clock pins I was now at gate on this will be an three. This is an N gate with three input and the output of the end gate will be the are put off the rebounds A circuit. This will create the D balance signal. I would invert the, um put off the last few flop on connected to one off the input off the end gate. The second input of the engage will be connected to the second free plop and the one on top will be connected to the first flop on the left. So this engaged. He's processing the output off these free plops to generate a D bounce signal, and I will rename the boats and here are the ports for clear and clock. 14. Implement an SR using FFs with a Debouncer - Practical: in this lesson, we will continue from the previous project with other the D bouncer to the design Off the shift register. We will make use off the D bouncer to create a post for the chip, enable pins off the shift register. So starting from the last project with select the D Bouncer and click on create schematic symbol with the tub designed, selected now and symbol, you will see that there would be one more category added on top. And if you click on this category, you will see that the D bouncer will appear in the symbols box under it. I with then click on it, then click on the schematic off the top module for the shift. Register to other D bouncer in the top module. I was a remove. The clock enable port and I will connect The are put off the D bouncer to that net. So now the D bouncer is driving the C E pins off the feet plops. Here we add a port for the input of the D bouncer, which will be connected to the push button and the D bouncer. We also need connection to the clock as whether as the clear and the input to the D Bouncer will be renamed to CNN under school DB, which is Glock. Enable de Bounced. I would have to modify the UCF to reflect the new name off the clock enable and I will also change the location off this. Got any bull to the push button? M four. Now I can save the project and run generate programming file. Once this is done, I can use impact and program of the boat. Now this push button is used for the clock enable. As you can see, when I press on the M four push button, the detail, which is on P 11 will be clocking at each push button. The detail, which is on P 11 will be clock in using the M four push button. Each time a press on it, the Pieter van will be clock in and you will be able to see the shifting happening 15. Multiplexers - Theory: in this lesson, we will learn about multiplexes. Multiplexes are useful in digital electron ICS. They are blocks that can be used to select one line from multiple lines in a circuit. Here is an example. Off a multiplex. Er we've input D zero and D one and it has an up put off. Oh, the S s zero is a selector. Two depending on the value off zero Isar D zero off the one we go through the metal, Alexa. So the output will be equal to the zero. When s zero is zero. Why the output will be D one When s zero is one. So the S zero is a selection line. For example, if the zero is equal to one and D one is good 20 and s zero is go to zero, Then the output as zero will be equal to the zero, which is one. Now, if you change the S two s one, then the output with select the D one. And in this case, we have D one is good 20 So the output will become zero. This is an example off a four input multiplex er d zero d one d two d three are input to Smith Black, sir while s zero and s one or selectors and oh, these are put and it also has an enable. So the stick an example. So I put the zero is when s zero and s one or zero. When s zero is going toe one and s one is good 20 are put with the D one. When s zero is good to zero and s one is one. The Arquit with me d to when both as zero and s one has got to one. The output will be the three. If the zero is one. D one is zero. D two is one and different off zero These other interest and selector as zero is zero and s one is one 10 is too. So the output will be. Did you which is one? This is an example of a multiplex. Er we've eight input. So they are the zero to D seven on the selector is zero to s to. So the reason I have free selector s zero to s two is because I have eight input. I need to choose among eight input to the power of three is eight. That's why I have three input for the selector. This truth table gives our print for each one off the selector combination. 16. Implement a Multiplexer - Practical: in this lesson, we will implement a multiplex er on the board. I've created a new project and I've added a new source which is a schematic and in categories I would choose marks. I was set like the marks and four on the school one e and drop it on the schematic. Are we? Then add ports to the input and output. In this case, we have input these euro two d one. These are for the data and for the selector have s zero s one and there is also an enable as well as an output. I will rename the detail Input boat do in 02 in three on the subject will be SCL zero and s year one for the enable. I would simply add a pull up. This will keep the enable one all the time. In other words, I'm not using the enable line for the output. I will rename it to out zero So the design is done. I can now add the constraints file project new souls implementation gone strings fire the gun finish how the UCF here I will add the net in the lock as we've done before. So we have input in zero in one into an entry. And we have the selectors SCL zero s year. That one and we have our put. I put zero out. Zero n zero to n free will be locked to the stretchers P 11 to before the select polls will also be connected to see Cher's Eat you and N three. While the output will be M five, which is a lead on the board, I can now run the generate programming file. Once it's done, I can use impact to program the Bold with that a bit. Now, this is a little demo or how the much back sir is working. So the M five is our put off the magic back, sir, The select input will be on the left to switchers. If I select 00 on the select input, the output will be equal to the D zero. If I said like 11 the output will be he go to d three for once. You it will that the second are put. Go out. Why 01 the airport where they could to d one, which is zero in this case 17. Counters - Theory: in this lesson, we will introduce the concept off counters in Banbury. This is a calculator. I'm doing the calculator on programming view. You see, there are a couple of options hex for Hexcel Ismael the easy for decimal opt for upto on being for binary. These are the number systems that we normally use in programming or digital electron ICS. If I set it on dismal and I write 12 then I click on being by Neary. You see that the two of you change into 110 So 110 is a January equivalent off the decimal number 12. If I put it on to the boundary, he's 10 The do is equivalent to 10 If I use five in decimal the binary echo violent. He's 101 If I do zero plus plus one on the calculator and I continue pressing on equal, the equal sign will make it count up. So you have incriminating off the number now if I said it to been and I do the same plus plus one and I keep pressing on the equal sign, even see that it will count up in binary. So this is a counter in binary, and this is what will be implementing on F p G. Hes A look at a couple of counters that we have in the symbol library in I see the 1st 1 here is a two bit counter, so Q zero and Q one would be the upper. It and the TC is a Carrie. Carrie is when the maximum count has reached, the curry will be sent to one. Why, when it's not reach the maximum, it would be at zero. So it also has a chip. Enable ka cable on the clock as well as a clear. The 2nd 1 is a four bit counter que zero to queue free. We are put the account so this will be a four bit binary number at each clock cycle and with increment one time. It also has a carry d. C. This one is an eight bit counter. So the number of bits that are put from this counter is eight que 02 q 7 At each clock cycle, the are put January would be incremental 18. Implement a Counter - Practical: in this lesson, we will see how to implement a counter on the board. This is a new project and I've added a schematic as usual. I've also added a UCF for it. So now I'm selecting counter in categories and under counter. I was like, See before See? So this is a counter that we will be using. Now I'm adding the ports and I'm renaming the ports that are put banya. We will be out zero to art three and TC will be the curry. - Now for the cuff enable, I will use the D bouncer so I would go in the project that I've created the d Bouncer copy the d bouncer dot sch and based it in our new project in the project directory. Then I would add this divine answer that I've copied into my directory into the project. Now it's under the D bouncer in this project, so I don't need to create a d bounce again. I just need to copy the file into my project, like in our click on create schematic symbol and in the symbol library. I will see this line appearing on top when I click on it in the symbols box. I will see the D bouncer. Are we quick on the divine answer and Greek on the schematic to other divine answer to it. Now we have to connect the our part of the D bouncer to the input See off the counter. I'm connecting the clock and the clear pins off the divine answer. And I'm adding a port on the D bouncer in which will be connected to a push button. We re name is a sport to push clock. The push cock will be generated from the push button. It's a good idea to clean up the project. Friends. Once done, I can edit the UCF with other net locks. Here are the output 02 out of three ce zero and TC. So this is how I look at the output and input. Once done, I can save it and generate the programming. Feiler. After that, I will use impact as usual. Program the boat with that a bit. Here is a demo off the design on the board. After resetting the counter, I can use a push clock to incriminate account. You will see that there is a Siri's off binary that is incriminating. Once a maximum house reach, you will see that the light on people will be set to one. This is a curry so resetting we reset the counter to zero. I can start over again. This is a binary counter implemented on hardware. 19. Adders - Theory: in this lesson, we will introduce the concept off others in digital electron ICS. As you know, numbers are represented in binary in digital electronics. So the others that we will be talking about or binary others. Here we have our calculator in the programmer mood. If I write 23 in decimal bless 56 it is good to 79. That's a normal way we do addition I went to do. Plus 88 is 110. This is all in the decimal number system. 45 miners, 23 equal to 22. This is subtraction in dismal. Now let's dry. 78 Bliss 12 in dismal abuse Me 90 in decimal. Now let's convert this number 78 into binary. So again, this 1001110 Now we know this number. So 78 in January is 1001110 Then we convert 12 into binary to 12 in decimal to binary. The 12 in January is 1100 So let's do the audition. We know in this small we will get 90. So let's check what's 90 in binary to 90 in January is 101 1010 So let's try the whole addition. In binary, we take this number setting the calculator. In January, I will enter this number 1001110 and I was added to 1100 And the answer is 1011010 which is 90 in binary. So this is an example where we've done an action in binary format. This is what a binary other will do. And in the next lesson, we will implement this in hardware. 20. Implement an Adders - Practical: in this lesson, we will implement a binary other on the F p G. This will allow us to add two numbers in binary. I've created a new project and I've uttered a bank schematic and a blank UCF are as usual. Next on the symbol Tamp are with Celtic arithmetic and under athletic. In the symbol list, I would add add four which is an other we then at the ports. As you can see, the R four inputs a zero to a three and under the four input B zero to be three. These are the two numbers that would be added by the other. And these numbers are four bit binaries. You will also see s zero to s tree on the output. These are the output bit for the some. So the some will be given by the forbid binary and there's also a carry out. This carry out will be set to one Onley in the case where we have action off to large numbers and we need 1/5 bit to represent us some. This is when the curry would be set to one. I was now renamed the ports and um zero to n M three will be one binary number one forbidden by any. Remember why that b and a school number zero to numb three will be the second binary number . This is the carry out and we have some zero to some three for the carry in. I was set it to zero permanently by adding a ground to it. This is because I don't want to use the curry in the carrion is used when you have cascading in a some. But in this case, we're simply adding two numbers. So we don't need this carrion. Now the design is done. I was now at the UCF Constraints Net locks. I really look the numbers in, um and Denham do speeches. Why, some zero to some free will be displayed on the lead as whether as the carry out, these are the locks that I will use. I can also project clean up and run Jared programming before once done, I will use impact Our usual. You go to the bit file on the board here we have a demo off the other on the board. So the structures we showed two sets off numbers. The four on the right on the phone. The left are two numbers, while the result will be displayed on the leads. These check two numbers. For example. Here we have 0011 purse. 1001 on The answer given is 1100 Please try different numbers and see if the other is working as expected. 21. Random Access Memory - Theory: And this is, um, we take a look at rooms, which are random access memories. Rooms are useful blocks in digital design because the other storing off information such as an image and audio file, any data or intermediate data in a piece off memory that can be written in and accessed by reading them out. This great represent a rum. And, as you can see the old zeros, these numbers are bits that are stored in that room. We can view a wrong as structured fit plops to store bits off information. Each row is one undress, for example. The first rule is 000 The second rule is 00 1/3 002 In this case, we have 10 columns, so we are storing 10 bits of information in 100 disposition. The run will typically have address input and an enable line and a data input. And the wrong will normally allow writing into the memory area or reading from the memory. So the address will tell where we are writing or where we're reading from, and the data will be the data that will be written in the memory. After a specific address space. Oh, it could be the data that's read out. In some cases, we have right enables, which tell whether we're writing or reading into the memory. This table shows that we have eight address locations and 10 beats per location so we can store 80 bits off information in that address space. Hes they look at a room from the symbol library school around be 16 and the school s one. So you will see that these WG that's a right enable input and that will determine whether you're writing or reading from the wrong. When W E is one, it means that we're writing into the wrong. The enable e N is for enabling the rum. There's a clock and we have two buses. One is a video which is address, and in this case it's 0 to 13. So it's 14 bit wide, so it's 14 bits wide while the detailed the eye is one bit wind 0 to 0. We also have a data output dio and this is also one bit wind. This is Rahm be 16 s four. So here the difference is on the address on the data input output the size of the address would be 0 to 11 which is 12 bits, and the data is 0234 minutes will be written in and four bits will be read out. So the number off addresses that would be available on this memory element is two to the power off 12 because you have 12 bits off address, so you have a new to to a power off 12 to get the number off address positions. So in this case, the answer is 4096. We have 4096 address locations and each location. All I was storing for mitts off detail. Now, if you multiply this number 14 96 times the number off data bits in one position for we get 16,384. And this is why the wrong is called 16. It's a 16 gigabyte data, Ron 22. Implement a RAM - Practical: in this lesson, we will implement a block room on the F B G after today. New project. We've a blank schematic and a blank UCF. I will copy the D bouncer That s C hedge into our new project. I was simply paste the demands and that s a hedge. Then I would do project at New source and I would find this Defensor in my project directory and added to the project I would say, like the diva answer and create a schematic symbol. And after that, I will find in the categories that there will be under the line added on top. And if I said exists nine, I would see the d bouncer clicking on the D bouncer and clicking on the schematic with other divine answer on the schematic. Then I will add a counter by selecting counter in categories and then selecting the c B four c added to the design. And thirdly, I will add the block around by selecting memory in categories. Then in the list of symbols under it, I will add rum. Be 16 on the school s for the counter would be used to provide the address to the wrong And the D bouncer will be used to increment the counter. I was under ports and connect the wires. De bouncer out is going to the sea. This we create one person. Each time I press the push button, the clocks will be linked together and I will have a cock port. I would also connect the clear pins together and for the ram. The clear is called S s are just clear the output. It won't clear the whole content off the memory. We have a data input port and this will be a bus. So we have to rename it in the following way. This is a push button input that will increment the counter that would be used to create a pills for the counter. This implementing the counter for the address off the wrong. This is the right enabled bin. When this is set to one will be writing in the wrong. While when it's set to zero will be reading from the wrong Are the fix the N after one? We won't be using the enable pin off the rum. This is why I've added a pull up to provide the address in this case. We have four pins in the simple for counter for the output while in the symbol for the wrong address. The address input is a bus, so we have to connect it in a particular way to connect the four pins together and make a bus so that we can use it as a bus for the address in foot. We have to make use off a bus stop in the filling way. And now that the design is done, are we? Look, the UCF asked for those after that, I would save and project clean up. Then I would run Jerry programming Feiler. Once it's done, I would use impact to program the bit file on the board. Hes a demo off the wrong on the board. The second switch from the left will be right, enable when it's high. Are we right in the memory? I've set the right enable to one so I can write some data in, and I'll use the push. But on the first push button to increment the counter and cock the data on the wrong. So I'm entering a series of data, clock them into the addresses, and then once I'm done, I will set the right unable to zero. This will allow reading the detail out. Then I would have reset the counter to all zeros. So you will see that the data that you've entered when you are writing will be cooked out. The same data will be clock out. So please note the patterns or you can write the battery on the piece of paper. Then you can read them out and check if the data all the same. So what we've done now is to store some data on the run and read the same detail out. 23. Finiste States Machines - Theory: in this s on. We will take a look of finance States machines fine United States machine or FS EMS are part of the design techniques we use in digital electron ICS. In some cases, it might be best to represent a design or part of a design as being made up of states. This part of the design can transition from one state to the next, depending on certain input. And this actually give you several examples of how efforts um can be used. Here is a block diagram. Off age Eric Finite States machine. As you can see, there are three sub blocks. We have transition logic, state memory on our put logic, the state memory with stole the state off the finance state machine fs um, using flip flops or in some cases, you can use rums. But for this course will focus on viewing the state memory as flip flops. We also have the transition logic this wisdom in the next eight. Depending on the input on also the present state, the output logic will determine the output off the FS. Um, based on the present state, in some cases, in terms of input, Now we give you several examples. You understand? What's an F s? Um, in this example, we have two states locked and unlocked. These are represented by circles and in beating the circles we have arose, for example, from locked. Do unlock. We have coin going is an input the interstate locked. If I get the coin input, if we truncheon to unlocked. If I get the push input from locked, it will stay on the locked from unlock if I get it. It was the It will stay in the unlock state from a lot. If I get push, it would go to a lot state. This is how we should understand a state diagram. The next example. We have four states. Start state one state two and state. And from start to state one we need truncheon One. This is an example where we have two states that off and let on. If the time expired from lead off. If we go to that on from that on, if time expired, it will go to that off. Hey, we have open and clues to states. This is a more complicated example. We have several states and several transitions. Now let's take a look at 77 has three states A, B and C, so the number of states is free. So what would be the minimum number of bits needed to encode the states? I'm so used to now This is because two to the power off two is four, and here we have three states. So with two bits, we can code up to four states. And this is enough to represent three states that we just need. Duthie plops as minimum to do this job. So we have three foot tops. We can represent eight states. Two to the power of three is eight. Now what's encoding. This is an example of including state A has been encoded as 01 stayed me 00 and state see 11 state A. This means that Q one is zero on Q zero is one. So when Q one is zero and Q zero is one, it means the FS um, is in ST A. If both Q one and Q 00 it means the state is state be. And if q. One and use you at one. The state is see. So that's how we use a fit plops to represent states, and this is called encoding. Now, there are two types off Fs Um, we have them move on the meaty more machine and the meeting machine. A defection for more machine is an f s. Um, whose are put depend on on Lee the present state. Here is a comparison between me the machine on moon machine. The first line we see are put depends Both have been present state on present input while for the more machine, the upward depends on lee Upon the present state, the second line merely machine has fewer states is on move machine third line are put changes at the clock edges one for the moon machine input change can cause change in the output are soon as a logic is done and the fourth line mealy machines react faster to input while move machine requires more allergic So it's a bit slower now this take a look at a state table. So you have present state this table represent the transition off the states and how the are put depends on the present state and this is just from the diagram. So from this diagram, we would be able to draw this stable from sting Be if the input is zero stays at me. If the input is one in goes to D. This is what it says on state. See if you get one. Stays on, see if you get zero. It goes to D from State D. If you get 01 it would stay on state D. The full fine. This is how we should write the state table. Now for a media machine, the output will depend on the state as well as input. That's why we have more entries from State A. It goes to state B if the input is zero and also that I put its X one then putting zero from the state A in ghost of states. See if the input is one. The are put with me X for the input one from me be to be input. Zero on the output is X two and goes to D one. The input is one and I put out different in the furthering lessons. We with design and efforts, um, from scratch and the concept off state diagram and state table will be clarified 24. An example of a Finite States Machines: in this s, um we will take a look at an f s. Um, example. Well, look on the fs um state Dan Graham. We'll also open the efforts, um, design in. I see and try to understand the different logic in the design. We really identify the state memory logic, the transition logic on the airport logic. The example that we really work we've is a home alarm system. The state diagram with consists of three states alarm locked and unlocked. The default state would be unlocked when it received the lock signal. It will move into the lock state from the lock state if it's sensor signal is up, pain even moved to the alone state from the lock stayed. If it received an unlock signal, it will go back to the unlock state and also from the alum State. Receiving an unlock state will move it from the Alan to the unlock state. So the home alarm system We have states alone locked and unlocked. It would have intuit look, unlock and sensor. So once it's locked, if it received a sensor signal, it will go in the other state. The output will be alone, locked and unlocked and these free would be connected to output lent. So we have one that for a loan one that for locked and wondered for a lot as we've seen before. The finite state machine consists of three parts of ST memory transition logic and are pretty logic. We will identify this free logic in our design. We also see the input and output. This is a design that is provided in this lesson. Please unzip it on. Open it in. I see. So that's taken at the UCF. So in the UCF UC input sensor lock unlock, we have clear and clock input and we have our put locked, unlocked and alone which are connected to lens. While the 1st 4 input in the UCF will be connected to speeches. Let's take a look at the schematic. First thing that you will notice are two flip flops, so these flip flops will be part off the state memory. So we need to fit flops to encode the three states. The clock goes into these fifth ops and they also have a clear Now we have three input, lock, unlock and sensor. These are shown here and we have our put unlocked, locked and alone. Now we have two sets off allergic, this one and that one. This will provide the next state logic. That is the transition logic. They will processes the input on the state, the current state, and provide the signal for the next eight that these will go to the input of these fit plops. Do you have to signals one is going to want to plop and the other one for the other fifth up. So these are the transition allergic, and now we will see the are pretty logic. You will see that the input will take signals from the cue off the flip flops and use some logic to produce the are put signals again. Generate the programming file after this and test it on the board to see if the design is working properly on the F b G. These note that the structures that has been used for the input because you would have to use them on the board. The sensor is locked two p 11. Look to em for unlocked to see 11 and a clear to a seven. I also, you have to understand which are put. Lead is for which our food port locked is an 11 and lock em five and alarm p seven 25. States Transition Table: in this lesson, we start to design the efforts. Um that we've looked at in the last lesson from scratch. Now this is the state table. We will design the efforts, um, as a more machine on this table. The column on the left is for the states. We have input next it and are put. Now, let's try to understand this stable from the state alarm, we see that this line shows one x x the x x or use ours Don't cares. So when unlock is one And what if the lock and sensor input or act from alarm the next state will be unlocked and our could we be alone so that there would be an alarm. There won't be a signal for locked and unlock, but just for other to the X are don't cares. In the second line, it says zero x x So if we receive anything from Alum and the unlock is zero, so we don't care the input for walk and sensor, it will stay on Alum so along we keep going on. If the enough is zero as long answer unlucky zero along honesty in the state of alone. Next we look under state locked, so from locked. If it receives a sensor, we don't care about the unlock and lock. It will go straight away to other and on that state, the lock that will be turned on so irrespective of the unlock and look if the sensor is one from locked. So if you look at your house, if there's a sensor signal, it will go straight in the other. This is what this sign will do on the state of luck. If there's an unlock and there's no sensor, so zero on sensor and unlock why lock signal is they don't care. X one X you were lead to unlock, so we will unlock from a lock state if there is an unlock signal and that is good to one. If there's no sensor input, it really good to unlock and the third line for luck. If both unlocked and censor or zero, there's no signal coming from the sensor and no signal coming from unlock. Whatever lock is the state with me locked, so it will stay in the lock state for unlock. If there's a lock signal irrespective off another and sensor, it will goto so Even if the sensor is one, it will go to a lot from there. If there is a sensor, then it will go to alone. And the last line from the unlock state. You will stay on the unlock state if Locke is zero, irrespective of the other signals. No, this is how we code the fs. Um, I would use a full, including alone 11 unlock 00 and look 10 I just use arbitrary coding. But there are techniques that are used to determine what is the best, including for a state diagram. But we won't go through this in this course. This is especially critical if the design is large, all there is a safety issue. But in our case, in just a simple design, so we don't need to care too much about this. Next, I will replace the album. We've the encoding of use here. I had alarm, so I'm using 11 for other one for a knock state. I'm using 00 And for luck State, I'm using 10 Same for the next eight. So I have including for the present state on Kolding for the next year. So every place all the alarm, unlock and lock text in the previous table by the proper, including that I've chosen. Now, in the next lesson, we will find the relation between the output and the input and in this case, the input of the present state C one and C zero as well as unlock, look and sensor while the output with me and one n zero alarms locked and unlocked. So for each one off the output, we have to determine the relation beating the input and the output from this will be able to determine the logic to be used in the FS, um, for the transition logic as well as the airport logic. 26. Equations for Transitions and Output Logic: in this lesson with a determined the logic that are needed for the truncheon as well as the input. We'll make use off the table and find the equation that relates the output to input. And from this we will design the logic. I will use this website 32 times eight that come. This website provides logic circuits simplification. So these other input c one c zero unlock look and sensor while the it could be anyone ends you at home and locked and unlocked to determine the relation Meeting the upward on the input. So, as we said in more machine, the output will depend on the under state and the state is made up off C one and C zero. So we need to variable. So please click on the two variables on top in the truth table on the website. See, one would be a on C zero with me. Me So we start one day one so one C one and C zero is 11 The album is one to have to set. Why to one when it's 10 the other is zero when it 00 the other one is zero as we can see on our table. There is no 10 so you can just put it as X. It's I don't care. This is a truth table for the Alum. So once we're done, we click on Submit. So the answer is, Why is got to me? So in our table it means that the alarm is good to see. Zero. This is the equation that we were looking for. So I'm noting the answer here alone is going to see zero. Now let's do for the rest. I'm resetting the truth table. So now we will work out the occasion for a lot. Now look, 11 is 010 is one So ones you're one for 00 it zero. And for 10 it's X. And for 01 there is none and tree. So I pitted elex on submitting I found the question Why is go to a multiply in the dot is much fine and be not so eight times be Not so a lot is going to see one. C one is me times not C zero. In this case, I'm just writing and ot not. And if you do the same for unlocked. You will find that and not is going to not see one that these are the output logic equations. Next thing we have to do is to work on the next eight. We have N one and N zero, so we have to determine the occasions for N one and N zero. And in this case it's a bit more complicated than the output because next it will depend on the current state C one C zero as well as the input unlock block and sensor. So we have five variables, so you have to click on the five variable on top and the drifted will we have 32 entries to to a power of five years 32 to Let's start with the first line in our table 111 x x So 111 and I don't care, don't care on lock and sensor and one would be zero. So all of these will be 0111 xx xx means whatever is unlock and sensor as long as you have 111 it would be zero the next. He's 110 x x and and one will be 1 to 110 x x. That's why I've put the full to be one because anyone is one here. Third line 10 x x one So ones you x x whatever, whatever one that we have anyone to be one So I have to set them to one So ones your X x one 10 x x one 10 x x one and 10 X x one set to one. Next we have 101 x zero and anyone would be zero The ones here one x zero Once you're one x zero 10 when x zero through. These are two entries and next we have a 100 x zero. So 100 x zero 100 x zero and anyone would be one of the ones you x Once there was your exit through. I said to one 100 x zoo set to one. Now we have zeros, your X one X and here we have 01 So since we don't have state 01 we'll set them two x. We don't have state in our table for 01 or just send them to X and for the final two lines . I have 00 x one x 00 x one x and this will be set to one 00 x one x So these four we was set to one 00 x one x and lastly, we have 00 x zero x and these are zero when submitting will have the equation. Why it is good to a C not plus a not de times day plus eight times been up times and this is how I'm writing it here. So a C note su on easy c is and look for not off the unlock See one, not times l. A times locked, see one things and not see zero times center that these other equations and for the last one is Ansaru. If you do it, you will have this equation. You will see the n zero b that equation. Now let's take a look at the logic and understand how the equation is translated. In that logic for a loan you're taking C zero, So C zero is going to alarm. Very simple. You're just taking the input off this c zero The second free plop and providing the other for the lock. It see one times not Caesar. So we have. And he's doing the time and we have not. This is an inventor, C zero or not And we need C one because this is C one and not Caesar. And we have the unlocked and not is not see one. Not is inversion see one. Not now. We have the logic for the transition for anyone. It was good. The input D. So this is providing the end one. So here we see or three which is a three. Input or get because you have addition off free products. So one product is C one not unlock. See one not and look bless, not see one times look and the third product is is C one times not C zero times sensor. So this is a logic that would be created from these end and or gate. And this will go to the input off the first, the flip flop on the left for the last one. And this is the three input and get of C one Nazis, you and sensor. So this is providing and one now for the next and zero and go to the input off the fifth up on the right. In this schematic, these look at the logic and compete with the equation to see how that was dumb.