Gate Level Simulation - an Introduction to GLS flow | Kiran Bhaskar | Skillshare

Gate Level Simulation - an Introduction to GLS flow

Kiran Bhaskar, Teacher

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5 Lessons (15m) View My Notes
    • 1. Introduction

      1:52
    • 2. What is GLS

      3:31
    • 3. Why GLS

      3:26
    • 4. Types of GLS

      2:43
    • 5. Bugs found in GLS simulation

      3:19

About This Class

Rising complexity, tightening schedules and ever demanding time to market pressure are pushing the industry to move to the next level of abstraction for design representation . Even after efficiently using RTL simulations for a couple of decades, the industry is still relying on GLS (Gate level simulation) before sign off. Advancements in static verification tools like STA (static timing analysis) and Equivalence Checking (EC) have leveraged GLS to some extent but so far none of the tools have been able to abandon it. GLS still claims a significant portion of the verification cycle footprint.

The course is an attempt to help students / professionals to quickly ramp up on GLS basics and help to understand the GLS concepts .


The course is divided into 5 lectures .

Introduction - Introduction to course objectives and course requirements .

What is GLS - Introduction to GLS flow and challenges in running a GLS simulation .

Why GLS - Reasons for running a GLS simulation

Types of GLS simulation - introduction to zero delay , unit delay , SDF simulation .

Bugs found in GLS simulation - common bug types found only in GLS simulation.

Transcripts

1. Introduction: Hello, everyone. Welcome to the gate level simulation. Siri's My name is Karen Bhaskar, and I'm working in the digital verification domain as a principal engineer. For more than 10 years now, I've extensively worked with setting up jealous simulation for teams, and today I'll be discussing about the need for jail assimilation, the different types of jail assimilation and the common buck types formed in jail assimilation. Before you start the course, let us understand the course objectives. The course basic objective is to help students and professionals to understand what is the gate level simulation, and the challenge is running. Get level simulation. Why there is a need for jealous, the types of dealer simulations and the bucks that our phone only doing good level simulations coming to the course requirement. You need to have a basic ASIC design flow knowledge and some digital verification knowledge would be helpful. Jealous still claims a significant portion of the verification cycle. Footprint, rising complexity, tightening schedules and ever demanding time to market pressure are pushing the industry to move the next level of obstruction for Busan representation. Even after efficiently using RP its demolition for a couple of decades, the industry is still relying on jealous for sign off advancement in sth tools and equal and check have leverage dealers to some extent. But so far, none of the tools have been able to abandon it. Gela still claims a significant portion of verification cycle footprint, so let us not waste any time and begin the learning journey. 2. What is GLS: welcome to the Chapter one of the gate level simulation series. Today we'll be discussing Watergate level simulation is so to understand, to get little simulation, we need to understand the floor. Get level Simulation is the simulation of the necklace, with or without delays, and takes place after the synthesis off the RTL court or post place and Road article simulation, which is a simulation off. RTL aims to check and verify the functionality and the source, which can be described in one or more hits. The languages get limits. Ammunition is used to check and ensure that the desert functionality is not lost during synthesis. So let us understand the get little stimulation floor. You will basically be getting a necklaced and then esteve from a bag and team. The necklace is basically the design representation, and the SDF is the delay file, which basically contains the cell. Delays on the part delays. So then, once you get this, you need toe basically run a jealous aggression. When is your this aggression passes? There is a sign off saying the product is ready for release. Jealous run fields, then you need to be. But when you re but it might be issues with your test bench, or it might be issues with the actual genuine timing issues. So the back and team needs to revisit their flow and generate a new necklace and this deer and you read on your jail assimilation the sign of the product, even though from the previous like it seemed like a simpler flow, there are a lot of challenges in running a jail. Assimilation. Morgan Logic simulators are all even based. This means that the simulator engine only updates the state of the design when the event occurs. Such a SEC blockage or in in Portugal in article simulation, this is generally once per clock cycle, and Artie, in simulations, are relatively fast in jealous because of the greater complexity off each element. There are many more events to calculate, and even in 00 unity less simulation. It will take much longer to run than an article simulation. When you add the actual timing delays, the number of events grew exponentially. So what this means is jealous is inherently very slow to run. So does not make sense to run all your discusses in jail, a simulation you need to identify the optimal lists off tests that you want to run to utilize jailers in discovering functional or timing books. So when when there is a timing issue in any of the nets in your jealous simulation, a nexus propagated and debugging, this ex propagation is not easy for a verification engineer. There are a lot of forces that are there in your test bench and one when the necklaces and rated. Sometimes there is a need to rework these chest pains because the the neck hierarchies are completely modified on the neck, naming changes in your jail assimilation. 3. Why GLS: in the last chapter, we understood what what to get. Little Simulation is in. This chapter will try to understand why there is a need for jealous before we understand the need for greater accumulation. Let's recap on the flow. Basically, you haven't article representation and you verify this article representation with your functional verification. And after the function verification is performed, you basically go through the synthesis floor and you have to get level. Metalist. So there are issues which can crop up during the synthesis are doing the logic equivalence checked and stu, which can only be checked in the get little simulation rather than an article simulation. So it's a necessary aspect off the floor. They're straight to understand some of the points in the next late, the public up and reset operational for design. So have you public up your chip and how to come. The chip comes out off. A research can only be checked in the gate level simulation. Your ideal simulation can basically take the functionality, but their timing can only be checked. Order. Get low assimilation. As a member mentioned in my previous leg, there are some limitations to the SDA. The ability of the SDA toe identify a synchronous interface. It is a good way to check that the critical timing part off you're a synchronous designs that are not checked by STE can be checked by you are get loved simulation aesthetic timing constraints such as your false part arm article parts. If your timing constraints are wrong, that means you're not timing sum of the parts in your design which may lead to issues. So this become this is where jealous becomes important as a sign off low for your S t a. The very fire dft structures There. The free structures are absent in the RTL and they get inserted during the synthesis flow. To verify this, you need a gate level simulation bullet estimation. So the power estimation can only be done on a necklaced. So you need a gate level simulation should be critical time in parts of the A synchronous design. As I'm concerned, this cannot be checked by the SDA and this has to be checked in your gate level simulation . You need to check if the design works at the desired frequency with actually lives in place , even though s THX this with timing. It is important to check because off the missing constraints that may be introducing the steer. My test to find out the need for synchronizer if absent in the design. So basically, this is if the synchronizes are missing on some of the next, it will generate X onto this net and that'll be next propagation which can be caught in your get little simulation. So these are some of the points that are important on why get level simulation is important . We will check in the next chapter on the different types of get level simulation. 4. Types of GLS: In the last two chapters, we saw Waters get level simulation and why they get little demolition is needed. In this chapter, we try to understand the types off workloads simulation. The first type of get level simulation is a zero delis. Immolation zero delay simulation means simulating in a net list without annotating any time in data. It is mainly meant for checking and validating the functionality of the design once it was translated into get level necklaced. In general, religion volition the specified block delays are ignored. These guns off simulations are much faster than simulation with timing and can be started. Arlene, Your design cycle When recklessness not get frozen or you do not have the timing information available, The zero Delis simulation can be enabled using Lee no specifies, which are by adding delay more zero in your common line. As I mentioned, the simulations are much faster than simulation with timing and can we started of linear design cycle. The 2nd 1 is Unity Lee Simulation unit. Ill assimilation operates on the assumption that all elements in the circuit process identical delay times, hence providing any random delay values similar to adding her unit daily this has an advantage that this is easier to implement, and then SD of simulation zero delay simulations can induce false risk conditions, and Gerald really loops. The simulator ignores all more. You'll pardon relay information and timing, check and converts all non zero structural and continuous assignment daily expression to a unit delay off one simulation time. So this is a trade off between zero Deal. A simulation on an actual history of simulation. The issue of simulation is an actual deletion volition where they're delays specified in the SDF. File is annotated into your nets of their design, and their timing checks are colored out. This type of simulation is much more slower than a zero delay or a unity less simulation, but this is considered as a sign off for the product, so to conclude, unit and zero really, simulation is used in at least two years off your design cycle. But the sign of the product you need to do STF based simulation 5. Bugs found in GLS simulation: in the previous few chapters, we understood what I get. Little simulation is where there is a need for get low demolition, the types of good level simulation, and today we will try to understand the common books that are found in your get level simulation, the most common bug that has found using in gate little time listening stick timing book using incorrect constraints actually, cause you're synthesis stool to create timing books and the same bad constraints are used in your SDA, so the same constant error will cause wrong claiming in your design. And this can only be caught in your jail assimilation. The second type off common but that is found in your little of simulation is your be 50 bucks. Usually our gear does not include the FDA logic, so these bucks in the FDA logic can only be formed in your getting a simulation. The second type is deep polit instruction book. Usually your ordeal is again not poverty inserted, so only a power of their gate level simulation can help to catch your power insertion box the district of common books that the phone is the if death book. If death is in your court, where article simulation uses one sort of if Jeffs different from the if deaf synthesis used. Alicia doesn't catch this as it won't suspect anything until you're on your get level. Similar. The second set is fortunate. Released Bug. What happens is the verification guys forget to remove or release all or some of the first commands, causing this to pass on their books to go on reductive. Jealous throws up compile error for most of the internal forces when signals are renamed to synthesis, with fuel forces remaining to be revealed on remote if possible. The third set off bunk is the motorcycle part book. For example, you have a chick with 12 cycle Marty sickle partners. Your source signal must be held stable for 12 cycle periods, and your destination flops must only capture the reserve addict well cycle and not earlier than later. The fort is the Delta deliveries condition. Occasionally, the article is run with zero R A unit delay blocking and non working assignment that included RTL dietary ladies condition. These are simulation are defects. If your source ideal simulates wrong, people will design their Cipto pass. Wrong. The assumption everything is okay okay, but their final gates will work differently than their RTL. This is a rare case. We're only a gls will detect burial silicon behavior mismatch. So, as described earlier get level simulation is and it's a cityville. You need to run. Get level simulation to sign off your product. Thank you.