Digital RTL design and Verilog interview questions - part1 | Kiran Bhaskar | Skillshare

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Digital RTL design and Verilog interview questions - part1

teacher avatar Kiran Bhaskar, Teacher

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Lessons in This Class

4 Lessons (26m)
    • 1. Introduction

    • 2. Logic gates and encoding interview questions

    • 3. Synthesizable verilog interview questions

    • 4. Setup and hold interview questions

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About This Class

Digital Design and Verilog interview questions is an initiative to help students/professionals who have basic knowledge of digital design and Verilog knowledge to quickly ramp up for an interview .

The course is structured as 3 part series addressing the following interview question/concepts .

  • Logic design and encoding Interview questions
  • Synthesizable verilog interview questions
  • Setup and hold interview questions

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Kiran Bhaskar



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1. Introduction: Hello, everyone. Welcome to the distant artier design and very long interview question. Siri's My name is Karen Bhaskar, and I'm working in the real estate industry as a principal engineer for more than 10 years now, and this is the part one of this series, and today I will be covering some of the basic interview questions that are asked in a digital RTL design interview. Before you start the course, let us look at some of the course requirement, so you should have a basic digital design background, some basic very lock knowledge and some logic design basics will be helpful. I just look at the core structure, as I mentioned earlier. This is an introduction series to the digital Design 100 a suitable for new students and professionals looking to get into the real estate industry. If you're already an experienced designer, discourse may be helpful to brush up your skills before an interview coming to the core structure, I will take you through some of the common interview questions that are asked on logic. Gates and including wants inter sizable, very low corn questions and set up in hold interview questions coming to the course objectives the courses to help students currently having basic skills in very long or digital designed to people. In ample for an interview, I have been doing the same with my LinkedIn profile, trying to post regular interview questions to help cover a broad range of concepts. So let us not wasting your time and begin the learning journey. Thank you. 2. Logic gates and encoding interview questions : Hello, Everyone coming to the first chapter of the series, we will be discussing about the logic gates and courts. They're just making coming to the first question and one of the common questions that are asked for Fresh Air's who are joining the industry is implement logic Gates using tools to one marks. So here I have a implementation for an and gate. So for an and gate you have the X and why they exist connected to the select line and vice connected to the Selectmen. So when excess zero zero is always selector and Minnix is one why you selected this? Is another representative Shin off doing the same thing? Second question is on the north gate. How do we do an or gate using a twist? One marks. So here we basically can empty X to the select line on Viber toady zero in Children excess one always zero selected. So that is the nor get here When is one all the sexists zero and when excess one by by the selected coming to the 90 gate. It's a similar logic here, So when excess zero always one is selected so various nine here. Okay, there's no around here. But when excess one my body selected, taken, probably product table and see how this implementation matches. These are some of the other gates. For instance. Here we have X our gate. So for an extra gate, you need to cook connect X to the select line and way to zero point. And why Barto the one output. So, for instance, when x zero and why use zero that this 000 is zero when x zero and values one. So the next is you know, advice One said this one that is D X R. Get here a similar representation for X nor but hear why in my body is reversed coming to the not gate here you basically have an X here, so the select lane is connected to the input and you re gdi inverted output on Z. So when excess zero you have one getting selected onto Z, and when Nexus 10 is getting selected and this is an or gate So when excess zero n y zero, they're zero and when excess one and why is one one is selector and when X is one always one is selected so this forms to basic implementation off the unions still get using those 21 marks. The second common question of this court. Ask this. Build a forced to 1 march. Using her to is too one marks. This is a simple representation off her who were forced to one marks using her toast. One marks. So you have the four inputs here and one output here. There to select lines. Select zero is connected to the first stage off your marks and the select one is connected to the second stage off your marks. You can work this out by writing your trip table. The third question on logic Gates is given only two X. Our gate one must function is a buffer and the other as an in water. So how do we do that? So you have an xer and you have two inputs A and B. So for a buffer, the being put this selected to zero. So whatever is the value on a is held for our time and transferred onto all put away For an in mortar you have B s one and whatever this there on the input A is inverted onto the output Why 1/3 common question that disasters. What is great, Gordon? Where is it used? So to understand the difference between the binary code and Greek or they're just understand how do the presentation is? So you see that the similar number between zero and one, the binary in degree, have the similar representation. But for the similar to the representation or for by Nuri 0010 but for a presentation of Greek or changes here. So the whole concept off record is there is a single big change on every decimal change. So from decimal 2 to 3, there's a big change here and for this you must 3 to 4. There is a change here. So you if when you take all of the similar 15 representation, you have only single but change between did the similar numbers. So in the next leg we will try to understand the applications. So there is great cord used. This is mainly used in club coming, crossing. Think basically when you have to clock domains that are a synchronous to each other, I would like to synchronize the binary count from one, plug them into another, if every biggest changing this kind of creates a problem. So in clock domain crossing, usually recording is used in sort off by many, including on a day. Important thing is it consumes lesser power as there are lesser big transition. What's in a synchronous five for design? Great court pointers are used instead of binary pointer because they have to cross the plug domain question for another common question. That the draft refreshers is what is once complimenting compliment. So, for the ones compliment you basically inward, older bit senior, which stream So, for instance, the ones complimented off 110010 is 00110 on the two's complement is basically done by Eidinger one to the once compliment. So what? Is there difference? In one's complement, zero has two different representation that is a miner's zero and a plus zero. But in toast, Compliment zero has only one representation. Zero is always considered as a positive, and red is this once complement and does complement used. This is mainly used for signed binary numbers. It is used for science signed by energy are addition and subtraction. Thank you 3. Synthesizable verilog interview questions: welcome to the second chapter off the visit will design interview series. So in this chapter will be discussing about the center visible. Very lock or very log is a hardware description language, and there are a lot of nuances to its in tax. You need to be careful on. Have you called your very log? There does see some of D basics indefensible, very local. Coming to question one. The interviewer ask you to writer with a lock or for a simple, different club. So a simple D flip flop is basically, you have a D In port, you have oclock under your foot, so invade log you have on Always block. This is called the sensitivity list so that nobody sensitivity list value, insensitivity, less changes record. It's executed below. So the Q is latch release last night to the Cuban. A positive image of the clock occurs, so here you have your being put and you have a clock here. So, on the rising after the clock, Nadine POTUS flopped onto the Kyoto would second question is right. Every lock or for a different flop it a synchronous research. So here it is, quite similar to what we wrote before you have the sensitivity list now here in the sensitivity list, you have also de positive research coming in. So if you have a reset, you should be coming toe value of settling to a value of zero sq shirt lies the value off de. So here you have a clock B and Q so on reset here the value of queues full 20 But here on the clock, it's year value off DS sample onto value off. Q. The third question is to write the court for different elopement. Get a clock. So here you have a wired get oclock, which is basically on and off in a Berlin clock. So always on poster, Joseph, get it clock. That is what is going to the flip flop que was lashed onto me. So what happens here is the clock is basically gated. So many enable a zero. There's no clock negated clock is zero. And when on a gated blockage, cues sample onto the deal put. So either needs sample under the Kyoto. So this is another variation off the different club. Cordy Daytona were different flop, So basically, the court for this is always on posits off the clock When if enable is one, they should be last known to the U. How is this interface? You have a marks here you have a dean put and you have a cure Input when enabled. Zero The date eyes herto the previous value enable is one the date eyes last long toe The cure put Let us see the way from here. When enable is zero the queue is held stable. It is not changing with respect to value off D But when anybody is one on the positive, the clock, the value off the use captured onto the you are put. The next question is on a large implementation. You will be asked to basically demonstrate how where latch works and write this inter sizable court for so here You have since since it would release consist off Q and enable when enabled. It's one curious these last known to queue So when anybody is one, the value of Q is changing here and it is kept constant when Ebola zero and when inabilities pulled high again, the value changes here. The next question is on a who's the one marks implementation. There is a various were still writer who is toe one marks The simplest way is using their ordinary operator. What is their coronary operator is the ordinary operator is a question mark symbol here Basically even select is one when selected zero Hey selector when selectors one be selected onto T This is basically year A marks implementation No Max can also be implemented using a case statement like the one here So you have the sensitivity list here for a B or select line and you have a kid's select That is when selectors one you have one selector Select is here selector when selectors Udal or before you have be selected So the last center sensible called that I'm going to show today s t three and put parity in Corden marks. So you have here you have three signals a BNC and you have a select line which is off to bits If selected 00 you get selected to a selected 01 you get elected Toby else you get elected to see So here you see in the reform when selected 00 the value off Q is to value off a when 01 he changes to value off be. And when the risks value off 11 the cube basically gets selected toe the C value. So this pre success to the end off the center sizable, very local chapter. In the next chapter, we will see a bit more on set up in horror questions. Thank you. 4. Setup and hold interview questions : welcome to the Tor chapter off the digital design interview series. So in this chapter, Elber discussing about the set up in whore interview questions So she have already attended a digital design interview, Would have probably known that set up and hold is usually one of T Christians there. Disgusting that digital design interview. So let us try toe, uncover the concepts. So I assume by no most off your down no mortar set up time or overtime is but they're still not aware. I'll tryto explain briefly so set up Time is a time before the clock urge by which d the data to the flip love has to be stable and hold Time is basically a time window after the clock edge. That data has to be stable. Any violation between this Tubindo will creator Madaj stability. So let us uncover set up in whole concept using this diagram here. So here you have a launching floor under capturing Flop. So the data that has launched onto the launching flop goes through a combination apart and then re chesty capturing flop. So data has toe reach before the set up time before the blockage, and it has to be heard stable for whole time after the blockage. So what happens if I set up or your violation occurs? The fuck it goes into my job Stability photo award, murder, stability. We need to make sure that they set up in horror. Times are always respected. So let us see any question on how to calculate the set up in the whole time. So you have the Here you have the clock to kill. DeLay. This is the delay that is for the data to be launched from this flip flop. And then you have the propagation delay. The propagation delay is basically their time. It takes for the logic to propagate from this note to this north. And you have the set up time which needs to be basically honored for this particular flip flop or this particular circuit and you have the clock skew clock. Skew is basically their difference in the clock reaching this nor too this north. So, addition off all these should be less than the total time period. Let us see the question. No, for the whole time. So you have the clocked a que here and you have the propagation delay here, So this has to be hailed stable for he hold Bless, rescue. So this will give us a new question for So this case is the question for the set up. Slack set up slack is basically a T period minus a clock plus T prop plus tea set up miners rescue so positive set up slack means the D circulators not meta stable. And just a similar question for the whole select whole slack is basically a clock trustee prop minus the whole plus sq. If the whole slack is positive, that means there's still some margin available. Indie timing part. So they're just see some of the interview questions based on this concept. So coming toe an interview question and it never may ask you, How do you tackler set up violation in your security? So this is based on your setups. Lackey. Question the setups like it's basically people feared, minus ik o clock. Two Q plus D prop plus tea set up minus sq. So I set ups like has to be positive. Go away, Madaj. Stability in your circuit. So how can this be done? This can either be done by increasing the people here, which is indirectly reducing D clock frequency that your time your circuit what you have no , either play around with these things that this the Christy Clark took you or decrease the propagation delay off your combination part reduced to set up a requirement of the capturing floor. What increased the clock skew between the capture and launch clocks. So these are the ways to tackle set off violation. So we signed the lastly, some of their protest tackle set of violation. They don't see, in a really scenario, hold the system. So one of the operator says to increase the drive, stand off the data pathologic a celibate better drive stand can Charles de Lord capacitance quickly, resulting in the lesser propagation. Really? So your people up producers and you're set up slack turns positive. Use data part cells with less official rolled age. So you shall in your life cell library. There are the same cells with different racial religious. So you get if you yourselves without a shirt a shortage, it will have a lesser delay. Another approach is to restructure D data part. So based on the placement off data part cells, you can decide to either combine logic. Gates are split into multi state self so that the propagation delay can be reduced. Another way is to play video T clock. That's a largely sort of what you would probably do. Issue time your design ITER reduced frequency. So in the last two slight, we saw how to tackle set up violation. Now we will see how our hold violation can be tackled the whole slack. It's basically de Klerk took you plus t prop minus keyhole, minus disk. You? Yeah. So toe. Have a positive hold slack. You can increase the clock tick, you delay off the launching flop, decrease the holy requirement, decrease the clock, skew between the capturing cloak and the launching flop, or increased the propagation delay. So we will see some of the examples on how to do this in the real world scenario. First we saw, we need to increase the propagation delay for to fix the whole violation. So what do you do? You basically insert delay elements is the same place that you can do to remove old violations. Another way is reduced. Drives Trent off the data plot. Replace this elevator. Similar selloff, less Graceland so this will increase the propagation delay off the cell and the other approaches as we sauntered up be you cells with lower to shortages for whole violations. We need to use cells with higher to shortages so that your propagation delay increases. Thank you. Another common into the question is what is false part in your design So false parts are basically parts that are not timed in your ste. This may not be time for different reasons. One of the reasons Maybe that that part is not possible architecturally. For example, if you're taking monks here, you have a select which is selecting the marks and which is also input for marks one. So intellect zero this spot This not at all possible architecturally so you can set a full spot on this design. So another interview question that is asked this usually under set up in whole time. So for that you need to remember the setups like a new horse. Lucky question. So if you set ups like and hold slack is positive, that means there is no set apart for violation. So from the figure Abu the T Pierre, it is 10 nanoseconds block took you is to be Prop Max is for the set up is one and excuse one. So if you calculate here the setups like comes or two plus 49 seconds. So there is no set up violation. Similarly, for the whole slack, you have blocked a que keep it up. He hold and disk you so the whole slack is also positive. So this circuit is timing clean. So this brings us to the end off part one off the digital design and very long interview questions. Thank you for your time.