## Transcripts

1. Introduction: Hello everyone. Welcome to the clock domain crossing interview question series. My name is Karen buskers and had been working in the VLSI industry as a principal engineer, have extensively worked in their digital VLSI end verification domain. This is the part one on the series. And today I will be covering some of the basic interview questions that are asked in their digital RTL design interview, electric T2, clock domain crossing. Before we start the course, let us look at some of the course requirements. You need to have some basic digital design background, some clock domain crossing knowledge, and some logic design basics would be helpful. Coming to the coast structure. This is an introductory series to club domain crossing and a suitable for both new students who are trying to get into the industry and for professionals who are looking to quickly ramp up for an interview. The course is divided into three main sections. The first section is our dressing interview questions related to clock domain crossing issues. The second section is addressing interview question really liberating to MTBE f to flop synchronizer and triplet flop synchronizer. And the third section is addressing related to synchronizers with feedback, mocks, recirculation, ang, the commonly asked divided by 3234 circuits. Coming to the course objectives Nikos is to help students who are starting their journey into digital domain to understand some of the clock domain crossing concepts and to help them ramp up quickly for the interview. If you are already following me on Linkedin, have been regularly publishing or Daley interview questions related to digital design to help cover a broad range of concepts. So let us not wasting your time and begin the learning journey. Thank you.
2. Clock domain crossing issues questions: Welcome to the chapter one of the series. Today I'll be discussing some of the common interview questions, Astana, clock domain crossing, related to the crop clock domain crossing issues. The first question that you might be asked in an interview is, what are the basic issues when they talk crosses from one clock domain tool on under clock domain. So you have a data here which is copying from a flip-flop from a different clock domain to a flip-flop in another clock domain. There are three major issues that we face. Fastest metastability. Second is data loss, and third is data in coherency. We will discuss these in detail in the coming slides. Coming to the second question. And one common question that is asked, what does metastability? So here you have to pluck domains or data is crossing from clock domain C1 to C2. So if a transmission of signal a happens very close to the capturing clock domain, the data from the second flip-flop may become metastable. So what does it mean? The data can either go to logic one or logic 0, and the output is unstable for a long time. What does that mean? That means there is a high current flow, which is not an ideal situation. And on the final output can sector to either a logic one or logic 0, which means the functionality of the circuit is compromised. So what happens when there is metastability? If the unstable data is vector? Several adopt policies in their design. It may lead to high current flow and even chip burn out. Different finite cones desert in different values of signals that we just saw. And because, cause they're designed to enter into a nonfunctional state, leading to functional issues. The destination domain output may settle down to a new value or may return to the old value. Or the propagation delay could be highly leading to timing issues. The second problem that we saw with cloud domain crossing is basically data loss. So here we see two cases where a different set of input data, because data bit to get lost. Here, C1 is twice as fast as c2 and there is no phase difference. The data on a is correctly captured on the destination clock domain. In this case. In the case here. Because C1 is twice as fast as C2, a pulse here is basically lost in destination domain b. The third issue that we saw with clock domain crossing is data in coherency. What does this mean? Consider a case when multiple signals are being transferred from one clock domain to another clock domain. If all the signals are changing simultaneously and the source or destination clock arrived close to each other. This may result in invalid value of combinations. Indeed destination side. We say the data coherencies lost. So if you see here, we have a bus off bit two bit wide. So here value 00 is correctly captured in the destination domain. But when it is a transition from 00 to 11, you see due to metastability, now y is going to 1-0, which is invalid, and later exactly downs to 11. This may cause functional issues in your circuit.
3. MTBF and synchoronizer questions : Welcome to chapter two of the series. In the last chapter, we saw some of the problems that we face when we cross-cut domains. In this chapter, we will see some of the concepts that are used to remove clock domain crossing issues and some of the basic synchronizers. One of the most common synchronizers that is used to resolve globe domain crossing is there to flip flop synchronizer. So here a signal from a clock domain, a clock is going into clock domain BY clock. So what the basic concept of a two flips of synchronizer is. Even if the first stage of the second synchronizer ghost metastable, It can be captured correctly in the second stage. So if you see here, you have D signal a_dagger, which is basically the signal that is going from domain one to domain two. So in the first clock, the BQ 11 goes metastable. But since we have two flip flops synchronizer. The second, the second flip-flop is able to capture the data correctly. So in the last slide we saw hover to flip flop synchronizer can be used to this all metastability, but is to flip flop enough or do we need to have more, more than two flip flops or D destination domain. For this, what is important is to calculate what is called MTB. Mtb F is basically mean time before failure. It is calculated basically with the equation which is one by F block into f theta into x. For most applications, it is important to run calculation of MTV f for any signal crossing a CDC boundary. A failure in this sense means across a signal that is passing to a synchronous flip-flop and continues to be metastable one cycle later. When it's sampled in the second stage synchronizer flip flop. Since this signal did not say sharply down to a known value after one clock cycle, the signal could still be metastable when sample and pass to the receiving clock domain. This causes potential failure to d. Corresponding logic. When calculating MTBE F, larger numbers are preferred over smaller numbers. Larger empty BF number indicate longer periods of time before potential failures. While smaller empty BF number indicate that metastable could happen more frequently. So if you see here, if you have a higher F block and a higher data changing frequency, that means it, your MTBE f.stop number is lower, which means the circuit can go metastable quickly. So, so my question from previous slide was when there's 23 flip-flops, synchronizers needed. For very high-speed designs. Dmt BF F2 flop synchronizer is too short. A third flip flop added will help to increase the empty we have coerce her satisfactory duration. Who decides this is usually determined by the architect of the design. Another common question that is asked is, do you need to synchronize the signal coming from the sending clock domain. The synchronous discussion of signal from sending clock domain reduces the number of edges that can be sampled in D, This you'd clock domain. This effectively reduce D data change frequency in D MTBE f equation, hence increasing the time between the calculated failures. So if you see here, the data is basically changing because there is a logic, combinational logic here. If this change happens very close to d destination domain, then it causes a failure. So it's always a good idea to have a, have this logic synchronized or D source before It's Cinco de destination domain.
4. Mux recirculation , Feedback synchronizer , divide circuit questions : Hello everyone. Welcome to the Chapter three of the series. In the last two chapters, we saw what are the issues that are faced in clock domain crossing and how some of the issues can be resolved using a two stage flip-flop and a three-stage flip-flop. And what MTB fs. In this chapter, we will try to dig deeper and understand different other synchronizers. The first question that you might be asked us, what should be the consideration that needs to be taken when you're synchronizing slow signals into fast clock domain. Usually synchronizing from slow domain to a fast domain is not a problem unless the faster clock is greater than 1.5 times the frequency of the slow clock. The fast destination clock. We simply sampled a slow clock more than once. In these cases, the simple too few flops synchronizer may suffice. So the next question is, what does synchronizer better feedback, OK, knowledge. So this is considered one of the safer approach for clock domain crossing. So the source domain basically sends a signal destination clock domain through to flip flop synchronizer, and then passes the synchronization signal back to the source clock domain through another two flip flops in quantizer as a fried buck acknowledgement, the figure shows the form of the synchronizer which is stored in the next slide. So this shows the waveform for the synchronization. Basically the ADA targets synchronized truer to flip flops synchronizer, and the data gets captured here on VQ to data on, after doing this off the clock. And then it is fed back to the clock domain. And after two edges and the data is received out Andi destination domain. So this is considered a safe approach for synchronization, but there is a penalty in d number of clocks that is used for the domain crossing. So in chapter one, we had seen a problem with D data in coherency. So this data in currency, can we basically use all using mocks recirculation logic? Let me recap on the data in coherency here. So basically you have the xo, x1, which is transitioning here and crossing domain. So the y of 0 and y, one, which is the domain crossed value, is going into, is going into invalid data here. So basically y 0, y one is now 1010 rather than 11, and it only gets captured here. So how can this be resolved in this can be solved using mocks recirculation logic, which is shown in the next slide. So the next question is, why is my mock, sorry, circulation synchronizer needed to resolve basically the data in coherency problems. So you have the solution domain here and a destination domain here. You have a bus of A1, which needs to cross her domain. To Vizio b1. So what happens is control enable signal is generated in social domain, is synchronized in the destination domain using a multi flop synchronizer. Synchronized signal enable sink is then drives the select pin of the maxes, thereby controlling the data transfer of all the bits off bus a. In this way, individual bits of bus is not synchronized separately, and hence there is no daytime coherency. However, it is important to ensure that the way that when the control signal is active, the source domain is 0 and E1 should be held constant. Another common question that is asked in the interview is D divided by circuits. So here we see a basic example of a divided by two circuit. I divided by 2a kit can be aroused by connecting the Q bar output. Offer D flip flop two D, D input. And you have done a French clock, and Q is basically d divided by two clock. So data friends, what happens here is on the Q bar is headed for complete cycle when the clock is, when you clock the D flip flop. So on every positive edge, the Q value, the Q value changes, which will give you a divide by two circuit. Here you have a divide by four circuit, similar to the divide by two, but you have two d flip flops. And you are dividing this by the French clock ones here and give aiding their friend's clock again here. So you're Q1 will basically be a divided four version of your base clock. So let us come to the final circuit. And most common interview question is to basically gravitate divide by three circuit. So this is a bit complex compared to the first two circuits that I shown. But basic approach here is past the second flip, flip flop, output to one more flip flop, triggered as the negative edge of the clock. So you have the reference clock here, you have the negative edge clock here. And you make an orange off Q1 and Q. This is required to achieve D divided by 350% duty cycle. Let's see how this works in this wave form here. So you have the reference clock here. Q 0 is basically a divide by two version of de, de France clock. And then you have Q1, which is basically a shifted version off d q 0 clock because you have a D flip flop here, you have a shifted version of q 0 here. Q is basically captured in the negative edge of the D flip flop. So you have a q here. And now what is done is basically an aura of Q1 and Q2. Q1 and Q is our together to get a divide by three circuit. Thank you all for your time.