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AHB and APB interview questions

teacher avatar Kiran Bhaskar, Teacher

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Taught by industry leaders & working professionals
Topics include illustration, design, photography, and more

Lessons in This Class

4 Lessons (31m)
    • 1. AMBA introduction

    • 2. AHB protocol

    • 3. APB protocol

    • 4. AHB interview questions

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About This Class

AHB and APB interview questions series is an initiative to help students/professionals who have basic knowledge of I2c  to quickly ramp up for an VLSI/FPGA/ASIC/Embedded interview .The course intended audience is beginners who are looking to get into the VLSI/FPGA/ASIC/Embedded domain .

The course is structured as 4 part series addressing the following interview question/concepts .

Part 1 - AMBA introduction

Part 2 - AHB protocol - Basic operation , Wait states , Burst transfer , INCR , WRAP ,MULTIMASTER AHB

Part3 - APB Protocol - APB interface signals  , Read transfer , Write transfer

Part4 - AHB interview questions 

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Kiran Bhaskar



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Technology IT Security Fpga VLSI

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1. AMBA introduction: Hello everyone. Welcome to the HB and ABB protocol interview series. Let us begin. Epb and HBR, a part of the bus protocol unbiased the Advanced Microcontroller Bus Architecture from the standardizes on-chip communication mechanism between various functional blocks for building high-performance associates. So here what you see on the x-axis are the different generations. So you have the b2, which comprises of APV and HB. This was the first introduced an MBA protocol. Iptv is used for low performance bandwidth. But if adults that are on your associates for higher performance was you have the HB, which is support 64 and 128 bits. And you have the HB light, which is for single masters. And then as, as the demand for high-performance grew, we also needed new protocols. So I'm introduced new protocols. So the next protocol was the AXI protocol. So the AXI is supported different address and data bus. There was burst and multiple outstanding addresses sign out of order response. And then we have D and D CHA protocol. So the focus of this course is more to discuss on the VPN protocol. Here is a small diagram which shows us the system level where these buses are used. You have here a system bus for HB and EPB. You have a central processing unit. The central processing unit operates on software, so it can be a CR, machine code. Anger at the hardware level when, for instance you have a load store instruction that gets executed. The load store instruction goes through the bus. So it can go through the bus and can fetch our data from an internal memory to do some processing in your CPU. So the HB and EPB bus are used for doing this in your SOC. What are the course requirements? The course requires you to have electronics, electrical, or computer science background. If you're already working in VLSI or an embedded system domain, that would be an add on. Coming to the cost structure will be discussing in detail or D ABB protocol and D must transfers. And then we will be discussing in detail about the ESP protocol in the frame transfer types in HB. And in the end there is a small section on interview question, common interview topics that are therefore the hedge being APV. Coming to the course objectives. The course is to help students who have basic background, the land electronics, electrical, or computer science, to ramp up to an interview for VLSI, Ember, Let's system domain. So let us begin. 2. AHB protocol: Welcome back to the HB and MPB introducing these. Today we'll be discussing about D is B, which is the advanced high-performance bus. Let us begin. So here we have a master and a slave connected through a HB bus. So these are some of the signals that are supported in which B we will go in detail with regard to these signals. So the master, since the signals to the slave, the decoder will select which live should be selected based on D, address information. Angry. On the receive side, the slave will send their data back. On HR data, hoodie, muster. Some of the important features of HBR, the bus transfer. And it is a single clock edge operation. This has a non-price straight implementation there configurable buzzword we will discuss in detail in these next slides. So these are some of the signals in d is we interface. You have D hedge clock and hit reset n, which are the global signals. And then you have the master out and sleeping signals. These are going outward from the Mastering into the sleeve. That is hetero address, which is the address hits, right? Which is telling whether it's a read write. And then you have hit W data, which is D data. And there are other signals like history, birds hedge, broaden hit strands to discuss in detail. And from this live, you have the hits, response, hits ready, AND which are data coming out from the slave back to the master. So this is the recap of the previous slide. We have the global signals, which is its clock in history certain. And then the muster out slaving signals which are hitch address and hit W data and all the control signals. And then the slave old mustard and signals, which is the data from this live and ready and that response. Let us now try to understand the basic operation of each bee bus. Here you have the addressing DataFrame is if you see here, addresses submitted every clock cycle. So because it's pipelined in nature. So for address a, the database comes in the next cycle. So here there is a read request and the data is coming out in the next cycle. And here it is, right where the addressing, address faces here and the data is given by the master to the slave. And the, because of the biplane nature DIE. Next Sartre says I'm retired in the next cycle and their data for this will come in the subsequent cycle. A hitch be like ABB has a concept of which states, the slip can start to assert wage states when they are not ready. So here you have the address space of u0, v0, it is read. The slave is still not ready to accept this address. So it puts D head's really low for two cycles. So the data is the data. He's coming out from slavery to the muster in this cycle. The consequence of this is the address space of B gets stretched. Here. There is another example where only one reached it is asserted. So similar to the previous example, you have the address. And this is a right in sort of a read. So the master says, gives the address and the data, the sleeve series. I'm still not ready to accept the data. So the data is kept for another cycle. The consequences of this, again is the address space of B is stretched. So here we have another example of DVT states. Here you have addressed a and it's a right. And digitize, produced here by the master to the slave. On the next cycle, the master adequate surrogate from a recipe. But for the next read, the slave is still not ready, so it pulls T heads 3D low. And the Data for b is available here and D hits reduce pulled high here. The consequence of this is the address, see the address phase of our dusky stretch for another clock cycle, and then the data see is produced to the slave. So let us now try to understand the four types of transfers. The fastest either transfer. So there is no data transfer require the slave must send the OK response without waiting, and tail must ignore the IDL. And then we have the BC. To insert idle cycles in a bush, you need to send a busy transaction. The BC will the burst, we continue afterwards. The addressing control reflects the next transferred into burst. The slave must again based with okay. And slow must ignore the busy. The next two important transfers or V, non-sequential and D sequential. The non-sequential is usually the first transfer of the burst, and it indicates a single transfer. The address and control are unrelated to the prayer transverse because it's the first transfer. And then you have these sequential in sequence here. The remaining transfers in the bus star are sequential transactions. The addresses previous or does plus the transfer size. We will see this in detail in the next slides. So here we have an example of F where we'd burst. As I mentioned, every transaction starts with a burst transaction starts with non-sequential trans type. So since this is the first transaction, the address and data is supplied here. So the next, the transaction will be a busy transaction. And then we have these sequential access, sequential axises. Basically. It's an ion CR birth, so it will keep incrementing by the transfer size. So here the transfer sizes a virtual, it keeps incrementing by address of four. So from 0 x 20 keeps incrementing 20, 24, and then 2018 to see. And here to here we also have an example of Wendy heads ready is Polo to insert a which state. Here we have another control parameter is just the head says this encodes the size of the transaction. This obviously cannot exceed the data bus width. For example, 32. The head size and hits versus determines D wrapping boundary for the wrapping bust. We will discuss this in the later slides. Head size must remain constant. Rotor bus transaction. Here we have the different head size. You'd have the bite half word, word, double word. So depending on the data bus width, we can define dy, hits eyes. And under control parameter which is important is the type of burst. Here we have different types of burst. The single bus does not biplane single axis. Then you have the IMC or burst which isn't increment, pink burst off undefined length. Then we have the rap for and IMC are for bursts and rapid NCI data and wrap 69 I MCS 16. We will discuss this in detail in the coming slides. Now you have the eye and CR4 bust. So here we have the address which is 0 X3 eight and the sizes of word. So every transaction increments way. Sizeof for so you have four busts here because it's an ion CR4, it starts from 38 and increments 2, 3, 4, 0 will fall and then it stops the burst. This is the basic ion CR4 burst. Here we have an eight beat wrapping burst. What is the wrapping? And wrapping busk always wraps around the byte boundary. So where it wraps around depends on the size. So for instance, here you have a rapid which maps 32 byte boundary. If it's a wrap for it wraps around 16 byte boundary. So for instance here you start to transaction enter 0 X3 four, after it reaches three, see it has Hindi boundary size. So it wraps around to the start of the boundary and then continues up till the prep is completed. So this is an example of a transaction. Another important thing to note here is D head size. So here you have an IMC or eight burst where it's incrementing for eight. There's a burst of eight transactions, but here the increment sizes to rather than 4 because the head sizes a half word. Then there is another type of bus which is D undefined lend burst. So here the master, the master gives the initial address N D HD size. And the worst keeps going, going on for an undefined length. So here it goes on from 05064 and it keeps going until it's terminated by D Master. So now we come to the last concept of the ESP, which is a multi-master. So here you have multiple master connecting to multiple slaves on the interconnect. So here we have an HB light master connecting to the HB light master here can connect to these three spheres in which we live. Master here can connect to these two slaves. Are these three slaves? How the accesses go through from this master to the disk lives depends on d, how the interconnect is defined. So usually we need a cross-border and knock to facilitate these kind of transactions. This brings us to the end of the chapter. We will discuss in detail on some of D is B interview questions in the next chapter. Thank you. 3. APB protocol: Let us start this course by understanding about the PPP protocol. Iptv stands for the advanced peripheral bass. Let us begin. So here I've underlined some of the most important concepts of the APV. Apv is used for connecting low bandwidth, but if it's a non pipeline protocol that can be used to communicate from bridge master to slaves through a shared bus. The read and write shares the same set of signals and there is no burst data transfer supporting MBB. As you can imagine, a B visa, low cost, low power and low complexity protocol. It has lower bandwidth compared to the other arm protocols. It has non pipeline and ideal for low bandwidth peripherals. They'd be WE protocol goes through three simple States. It is idle, setup, pen, access. Let us see what these different states are. At the beginning of the transfer, you have the B-cell NP and a well lo. And then we have the setup stage, the setup stages when the PCL is pulled high. And if it's a write access, their data is given here. And we write signal is asserted. And then we come to the exit state. The access status when PNA well is driven high, only other signals are kept steady during this state. So the slave when p enable is and PCL is high, it let us in the data if it's a write access, and then pulls d p ready to signal that the transfer is complete. So let us now try to understand the different signals that are there in D, a PV bus. So you have the clock and address signal. You have the right one signifies it's right access and GTO signifies it's a read access. And then you have the PWD, PWD ties de data returned to the IO device. This is applied by the bus master. Then we have the PCL. If we said is asserted, it means the current bus transaction is starting at 22. This device, if there are multiple sleeves on an APP bridge, so you will have multiple pieces going into the different slaves. And the address decoder basically be quotes and says which sleeves should be selected. And then you have the P and nibble. So it is high during the entire transaction at RND fast cycle. And then lastly we have d p ready, which is driven by the target. It is very similar to the UK that you see in some of the protocols. This indicates if the target is ready to do the transaction. Each target has its own POD, like each target has its own B-cell. You don't also has its own POD which goes back to the master. Let us see a simple right transfer with non-wage States. As discussed in the earlier slide, it goes through three phases. One is the idol phase, PCL, P enable is low. And the next setup phase where you clock in the address, right signal, select line and the data. And then you have the access fairs where your p.sit enable goes high and our data gets captured in your slave device. And the slip pulls the purity Lucene. I am ready to accept another transfer. So this is the basic re-translate will know which states. So let us see a weight transfer with which states. So the master says I want to write an article. I want to write to a particular address with a particular data. And it goes to the setup phase. But the slave acknowledges seeing that I'm not ready to accept the data and it inserts two-way streets. So the master has to wait for two cycles before it can send the data and address. So when the slave is ready, it puts the period the high, and the data is latched in. It pulls the PRD low for the next transaction. Let us now see how our retransmit works. In EPB. It is pretty similar to a right transfer, except doc after the address phase or the setup phase where the address is given and the PCL is selected high. Your pre-write will, in this case go low because it's a read access. And then the p enable goes high. The sleeve will produce the data to the master and the POD goes low for the next cycle. So this is the basic rate transfer with each stage. Now let us try to understand the returns fall with which dates. So here you have a pretty similar approach. You have the B-cell going high and the P enable going high, and the master is requesting read from address one. But this leaves is still not ready to give the data, so it inserts which states. And the period he goes high. The data is given from slave to the master. And the then pulls d p ready AND peter De Lu and the master push D P, enabling the PCA low. This is the basic transfer with wastage. There are other signals in the APV protocol which we have not discussed. There is another signal called decrease liver. This is an optional signal. So we can either tied to 0 or can drive it high if things go bad. And then we have the preset n, which is the active LOS system research signal. And this is needed for only peripherals. So this brings us to the end of D ABB protocol chapter. Thank you. 4. AHB interview questions : Hello everyone. Welcome back to the HB interview question CDs. Let us begin. Let us begin with some of basic HB related questions. Should hedge protein hit says, and hits rate remain constant throughout the burst? Yes, because these these are control signals demonstrating constant throughout the duration of the burst. The next question is, what is the default state for hits radian hits response output from this live. If you remember, It's radiant. His response are going as outputs from the sleeve and coming back to the inputs has mastered. So after research that default value of hits really should be high and the default value of hits responses, okay? So the master can send data to any slave. The next question is, what is the recommended default value for each plot? Which, if you remember from the CDS, is basically providing the production information. The recommender default value is non cacheable, non-profitable, privileged your taxes, which corresponds to four sig be 0011. Coming to the next question, how many masters can there be in the system? Each be caters for up to 16 masters. Allowing for dummy master means a maximum number of real bus masters is 15. By convention, bus master 0 is always a WBS muster. We will discuss in detail a wooden me bus mustard in the next slides. Wasted amine bus master, even necessarily. A dummy mustard is necessary in a multi-master system where the sleeve can give split transport response. A dummy mustard is required so that something can be rendered the bus if all masters have received the split response. This becomes important in a multi-master kind of an environment. Next question is, what is the state of a hitch be signals during the research? From the spec, it states that during the research by signals should be it valid levels. This simply means that the signal should be logic 0 and logic one and not high-Z. The actual logic levels driven are left to the designers. The headstands is the only signal specified during research which is mandatory value is idle. It is also important that hits readies high during the research. If all the slip system grave hits ready high during the research that this will ensure this indicates because it's it is multiplex to the master. However, if sleeves are used which do non-tariff, it's pretty high during research, it should be ensured that slave, which do not drive it's ready, hired is selected a, D, the cert. Another tricky question is, Is hits radian input or an output from a sleeve? And the HB sleeve must have hit steady signal as both an input and output. If you see here, there's a history input and also hits ready out output. The hatred is required as an output from sleeves so that this ligand extended data phase, the history is also recorded as an input so that we can determine when the previous selected sleeve has completed its final transfer. And D fast database. So when there are multiple slaves, you might have other sleeves which are gray Monday hits ready. So these needs to come in as an input to the slave so that you can understand when the previous electric sleeve has completed its transfer. What is the default state that should be used from its treaty in his response or port from a slave. The recommended default value as described before is hits readies, high-end hits responses, okay? This ensures that slave will respond correctly to either transfers event if slave is in policy anymore. Next question is, can we muster be connected directly to an HB sleeve? In each layer which does not use corresponds can be directly connected to a master. If this label does not do this split response, Dennis simplified what is enough arbeiten is required. If a masters directly connected to this layer, it is important to ensure that slavery lives hits ready high during research and the select signal himself from this slave is permanently high. The next question is, when can a rebus termination occur? The burst can be terminated either as a result of a Biden win the hedge grant to the master partway through the burst or a Slave written in nano corresponds to a beat of bursts. Note, however, that the master cannot decide to terminate a defined land burst unless prompted to do so by our Beta or slow response. All masters in sleeves and arbeiten must be designed to support early bus termination. The next question is, does the address have to be aligned even for either transfer? What is our dress? Alignment? There does, is usually a line based on the head size. So the address should be aligned even for either trans transfers. This will ensure that spurious warnings from bus monitors during simulation. In the previous chapter, we, we saw what are the different kinds of bus? We have a rapid burst, we have IMC or burst under undefined land bust. So when we add, are these different bus used? Typically, a master would use that wrapping best for cash landfill. This is where the master want to access the data request first and then it completes the birth to fetch the remaining data request for D gasoline fill. The IMC or bursts are used by master suggests and DMA controllers that are filling a buffer in the memory which may not be aligned to a particular address boundary. So if your memory is aligned to a particular address boundary, it is important to use that happening burst. Else, we can use a Eigen CR boast. The split. What is the difference between split and retrain in which we the fundamental difference is in how the priorities are S2, D0, masters. So in a split response, it tells the reader to give priority to all masters until split transfer can be completed. Effectively ignoring all for the request from the master until these blitz live indicated can complete the split transfer. Whereas in the retry response, it does the arbiter to give priority to the highest priority master. This brings us to the end of HB interview series. Thank you for your time.